ISL6423B Intersil Corporation, ISL6423B Datasheet - Page 11

• Manufacturer Part Number: ISL6423B
• Description: Single Output LNB Supply and Control Voltage Regulator
• Manufacturer: Intersil Corporation

START
SDA
SCL
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 6).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6423B will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
FIGURE 6. ACKNOWLEDGE ON THE I
MSB
1
2
11
8
2
C BUS
ACKNOWLEDGE
FROM SLAVE
9
ISL6423B Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
System Register Format
All bits reset to 0 at Power-On
Transmitted Data (
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR2 thru
SR4) of the ISL6423B via I
the microprocessor as shown below. The spare bits of
registers can be used for other functions.
• R, W = Read and Write bit
• R = Read-only bit
S 0 0 0 1 0 A1 A0 R/W ACK Data (8 bits) ACK P
SR3H SR3M SR3L
SR1H SR1M
SR2H
R, W
SR4H SR4M SR4L
R, W
R, W
R, W
read (1) or write (0) transmission) (the assigned I
address for the ISL6423B is 0001 0XXX)
SR2M
R, W
R, W
R, W
R, W
TABLE 5. COMMAND REGISTER (SR3)
TABLE 6. CONTROL REGISTER (SR4)
TABLE 3. STATUS REGISTER (SR1)
TABLE 4. TONE REGISTER (SR2)
TABLE 2. INTERFACE PROTOCOL
R, W
SR2L
SR1L
R, W
R, W
R, W
I
2
R, W
DCL
R, W
C
R, W
ENT
OTF
EN
R
bus WRITE mode)
2
C bus. These will be written by
VSPEN
CABF OUVF
R, W
MSEL
R, W
R, W
R
R, W
R, W
R, W
TTH
R
X
VTOP
ISELH ISELL
R, W
R, W
R, W
OLF
R
X
April 10, 2007
2
C slave
VBOT
FN6412.1
R, W
R, W
BCF
R, W
R
X