ISL6526 Intersil Corporation, ISL6526 Datasheet - Page 11

• Manufacturer Part Number: ISL6526
• Description: Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: Intersil Corporation

The maximum RMS current required by the regulator may be
closely approximated through the following equation:
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge currentrating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6526 requires two N-Channel power MOSFETs.
These should be selected based upon r
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see equations on next
page). These equations assume linear voltage-current
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6526
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Losses while Sinking current
I
Losses while Sourcing current
RMS
P
P
P
P
LOWER
UPPER
UPPER
LOWER
MAX
Where: D is the duty cycle = V
=
= Io
= Io
=
=
t
f
SW
s
V
------------- -
Io
V
2
Io
is the switching frequency.
2
OUT
IN
2
x r
x r
2
is the combined switch ON and OFF time, and
×
×
DS(ON)
DS(ON)
×
r
r
DS ON
DS ON


I
OUT
(
(
x D
MAX
x (1 - D)
)
)
×
×
D
2
11
(
1 D
+
+
SW
–
----- -
12
1
-- - Io
2
OUT
1
⋅
)
×
which increases the
+


/ V
×
V
---------------------------- -
1
-- - Io
2
IN
V
⋅
IN
DS(ON)
L
IN
–
,
×
V
×
×
f
OUT
s
V
t
SW
IN
, gate supply
×
×
×
V
------------- -
t
f
SW
V
s
OUT
IN
×


f
2
s


ISL6526
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised with devices
exhibiting very low V
through protection present aboard the ISL6526 may be
circumvented by these MOSFETs if they have large parasitic
impedences and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
boot capacitor, C
referenced to the PHASE pin. This supply is refreshed each
cycle, when D
the boot diode drop, V
Q
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
where Q
MOSFET, C
the bootstrap voltage immediately before turn-on, and
V
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
Q
BOOT2
LOWER
GATE
+
-
ISL6526
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
GATE
=
is the bootstrap voltage immediately after turn-on.
.
C
BOOT
BOOT
BOOT
is the maximum total gate charge of the upper
BOOT
GND
×
is the bootstrap capacitance, V
UGATE
PHASE
(
CPVOUT
BOOT
LGATE
D
conducts, to a voltage of CPVOUT less
GS(ON)
V
BOOT
BOOT1
D
, develops a floating supply voltage
, plus the voltage rise across
C
characteristics. The shoot-
+
-
V
BOOT
–
D
V
BOOT2
Q
Q
V
UPPER
LOWER
IN
)
NOTE:
V
NOTE:
V
G-S
G-S
= V
BOOT1
= V
CC
CC
-V
is
D