ISL6534 Intersil Corporation, ISL6534 Datasheet - Page 9

• Manufacturer Part Number: ISL6534
• Description: Dual PWM
• Manufacturer: Intersil Corporation

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Pin Description
VCC
This power pin supplies bias to the control functions. It can
be connected to a nominal 5V (±10%) supply, or it can
function as a shunt regulator (nominal 5.8V), with an external
pull-up resistor (nominally 150Ω to 12V).
GND
This pin is the signal ground for the IC. The metal thermal
pad under both packages is connected to the GND potential
(through the IC substrate; the pad does NOT substitute for
the GND pin connection). But the GND pin and the metal
pad should be connected together on the board, and tied to
a good GND plane (both for electrical and thermal
conduction). Note that the thermal pad on both packages
limits metal interconnect traces underneath the package.
VCC12 (QFN: VCC12_1, VCC12_2)
This power pin (nominal 12V) supplies the output gate
drivers, as well as some other control functions.
The QFN package has two power pins; one for each
switcher. They are electrically connected internally, but allow
for separate decoupling caps to better isolate the switching
noise, if necessary. Even if they share one capacitor, they
should both be connected externally, for lower resistance.
REFOUT
SS1/EN1
SS2/EN2
SS3/EN3
DRIVE3
COMP1
COMP2
REFIN
VREF
FB1
FB2
FB3
10
11
12
1
2
3
4
5
6
7
8
9
24-PIN TSSOP
TOP VIEW
SIDE PAD
BOTTOM
GND
9
24
23
22
21
20
19
18
17
16
15
14
13
VCC
BOOT1
UGATE1
VCC12
LGATE1
LGATE2
PGND
UGATE2
BOOT2
GND
PGOOD
FS_SYNC
ISL6534
NOTES:
PGND (QFN: PGND_1, PGND_2)
This pin is the Power GND for the gate drive circuits. It is not
directly tied to GND inside the IC; it should be tied to GND
on the board.
The QFN package has two Power GNDs; one local to each
switcher; both should be connected externally to the GND
plane on the board.
SS1/EN1, SS2/EN2, SS3/EN3
These analog input pins have two functions. A 30µA current
source charges an external capacitor (to GND), to provide a
soft-start timing ramp; their respective Output voltage will
follow the ramp voltage as it powers up. The 2nd function is
Enable; when the input is left open (with the soft-start cap),
the respective output will be Enabled after the ramp reaches
the 1V level. If the input is pulled to a low logic level, the
output will be disabled.
SS2/EN2 also has a special mode function; see Table 1.
Tying it to VCC (5V) selects the DDR mode (where both
OUT1 and OUT2 share the SS1 ramp); otherwise it will be in
the Independent mode.
COMP1, COMP2
These analog output pins are used to externally compensate
the error amplifiers for their respective regulators.
REFOUT
SS1/EN1
SS2/EN2
SS3/EN3
DRIVE3
6. BOOT2 and UGATE2 are different order in QFN.
7. NC is No Connect
REFIN
VREF
NC
1
2
3
4
5
6
7
8
32
9
10
31
11
30
32 LD 5x5 QFN
TOP VIEW
SIDE PAD
BOTTOM
12
29
GND
13
28
14
27
15
26
16
25
24
23
22
21
20
19
18
17
UGATE1
PGND_1
VCC12_1
LGATE1
LGATE2
NC
VCC12_2
PGND_2
FN9134.1