ISL6567 Intersil Corporation, ISL6567 Datasheet
ISL6567
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ISL6567 Summary of contents
Page 1
... PGOOD pin. Also included, an internal shunt regulator with optional external connection capability extends the operational input voltage range. For applications requiring voltage tracking or sequencing, the ISL6567 offers a host of possibilities, including coincidental, ratiometric, or offset tracking, as well as sequential start-ups, user adjustable for a wide range of applications. ...
Page 2
... Ld 4x4 QFN L24.4x4C ISL6567IRZ-T 6567IRZ - 4x4 QFN L24.4x4C ISL6567EVAL1 Evaluation Platform NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
Page 3
Block Diagram MON 300mV + 110% - 90% VCC 10μA 10μA OVP COMP 120% REFTRK REFERENCE VDIFF RGND X1 VSEN VCC VREG SHUNT LINEAR REGULATOR PGOOD FS EN VCC 20μA OSCILLATOR POWER-ON RESET (POR) PWM1 SOFT-START ...
Page 4
... R5 C1 COMP VDIFF R1 4 ISL6567 ISL6567 CHANNEL1 CHANNEL2 ISL6567 PVCC BOOT1 C BOOT1 UGATE1 PHASE1 ISEN1 R ISEN1 LGATE1 BOOT2 C ISL6567 BOOT2 UGATE2 PHASE2 ISEN2 R ISEN2 LGATE2 GND VSEN RGND HFIN1 C BIN1 Q1 L OUT1 Q2 C HFOUT C HFIN2 C BIN2 Q3 ...
Page 5
... System Accuracy (Commercial Temp. Range) System Accuracy (Industrial Temp. Range) Internal Reference External Reference DC Amplitude Range External Reference DC Offset Range 5 ISL6567 ISL6567 Thermal Information Thermal Resistance QFN Package (Notes 1, 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150° 0.3V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C BOOT - 0 ...
Page 6
... Lower Drive Sink Resistance NOTES: 3. Parameter magnitude guaranteed by design. 4. Not a tested parameter; range provided for reference only. Timing Diagram t PDHUGATE UGATE LGATE t FLGATE 6 ISL6567 ISL6567 = 5V -40°C to +85°C, Unless Otherwise Specified (Continued TEST CONDITIONS R = 10k to ground 10pF 10pF ...
Page 7
... NPN transistor and a couple of resistors to create a more flexible bias supply for the ISL6567. In any configuration, pay particular attention to the chip’s limitations in terms of both current sinking capability of the shunt regulator, as well as the internal power dissipation. ...
Page 8
... The potential at this pin is used as a clamp 8 ISL6567 ISL6567 voltage for the internal error amplifier’s non-inverting input, regulating its rate of rise during start-up. Connect this pin to a capacitor referenced to ground. Small internal current sources linearly charge and discharge this capacitor, leading to similar variation in the ramp up/down of the output voltage ...
Page 9
... FB R1 VDIFF VSEN RGND FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6567 VOLTAGE AND CURRENT CONTROL LOOPS Operation Figure 2 shows a simplified diagram of the voltage regulation and current loops. The voltage loop is used to precisely regulate the output voltage, while the current feedback is used to balance the output currents, I power channels ...
Page 10
... PWM OPERATION One switching cycle for the ISL6567 is defined as the time between consecutive PWM pulse terminations (turn-off of the upper MOSFET on a channel). Each cycle begins when a switching clock signal commands the upper MOSFET to ...
Page 11
... The upper MOSFET is kept on until the clock signals the beginning of the next switching cycle and the PWM pulse is terminated. CURRENT SENSING ISL6567 senses current by sampling the voltage across the lower MOSFET during its conduction interval. MOSFET r sensing is a no-added-cost method to sense current ...
Page 12
... Obviously, insure that the input voltage and all V OUTMAX the voltages sampled by the ISL6567 do not exceed the con- troller’s absolute maximum limits, or any other limits specified in this document. V ERROR ...
Page 13
... POR is released or the ISL6567 is enabled. The highest magnitude external reference fed to the REFTRK pin that the ISL6567 can follow is limited to 2.3V. The ISL6567 utilizes a small initial negative offset (typically about 50mV) in the voltage loop at the beginning of it soft-start, to counteract any positive offsets that may have undesirable effects ...
Page 14
... VOLTAGE TRACKING AND SEQUENCING By making creative use of the reference clamps at the SS and REFTRK pins, and/or the available external reference input, as well as the functionality of the EN pin, the ISL6567 can accommodate the full spectrum of tracking and sequencing options. The following figures offer some implementation suggestions for a few typical situations ...
Page 15
... Sequential start-up control is easily implemented via the EN pin, using either a logic control signal or the ISL6567’s own EN threshold as a power-good detector for the tracked, or sequence-triggering, voltage. See Figure 15 for details of control using the EN pin ...
Page 16
... Disabling the IC via the EN pin does not turn off OVP protection. START-UP INTO A PRE-CHARGED OUTPUT The ISL6567 also has the ability to start up into a pre- charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off ...
Page 17
... A first step in determining the feasibility and selecting the proper bias regulator configuration consists in determining the maximum bias current required by the circuit. While the bias current required by the ISL6567 is listed in the Electrical Specifications table, the bias current required by the controlled MOSFETs needs be calculated. The following ...
Page 18
... Figure 21 details such an implementation utilizing a PNP transistor. Selection of R1 can be based on the graphs provided for the passive regulator configuration. Maximum power dissipation inside Q1 will take place when maximum voltage is applied to the circuit and the ISL6567 is disabled; determine VREGMAX the obtained number to calculate Q1 power dissipation ...
Page 19
... The compensation network consists of the error amplifier (internal to the ISL6567) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F margin (better than 45 degrees). Phase margin is the difference ...
Page 20
... G ⋅ where MOD FB 20 ISL6567 COMPENSATION BREAK FREQUENCY EQUATIONS ). Figure 25 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted ...
Page 21
... Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. Although the ISL6567 allows for external adjustment of the channel-to-channel current balancing (via the R resistors desirable to have a symmetrical layout, preferably with the controller equidistantly located from the two power trains it controls ...
Page 22
... CONNECTION PATH) FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 22 ISL6567 important to place the R respective terminals of the ISL6567 multi-layer printed circuit board is recommended. Figure 26 shows the connections of the critical components for one output channel of the converter. Note that capacitors C ...
Page 23
... MOSFET is required to conduct, the switching characteristics, the capability of the devices to dissipate heat, as well as the characteristics of available heat sinking. Since the ISL6567 drives the MOSFETs with a 5V signal, the selection of appropriate MOSFETs should be done by comparing and evaluating their characteristics at this specific V bias voltage ...
Page 24
... Unfortunately, ESL is not a specified parameter. Consult the capacitor 24 ISL6567 manufacturer and/or measure the capacitor’s impedance with frequency to help select a suitable component. OUTPUT INDUCTOR SELECTION One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current ...
Page 25
... These capacitors must be capable of handling the surge-current at power-up. APPLICATION SYSTEM DC TOLERANCE Although the ISL6567 features a tight voltage reference, the overall system DC tolerance can be affected by the tolerance of the other components employed. The resistive divider used to set the output voltage will directly influence the system DC voltage tolerance ...
Page 26
... Package Outline Drawing L24.4x4C 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06 4.00 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 26 ISL6567 4X A 20X 24X ± BOTTOM VIEW ± SIDE VIEW ( 20X 24X 24X 0 ...