ISL98001 Intersil Corporation, ISL98001 Datasheet
ISL98001
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ISL98001 Summary of contents
Page 1
... RGB and YPbPr signals. Automatic Black Level Compensation (ABLC™) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The ISL98001 is fully backwards compatible (hardware and software) with the X980xx family of AFEs. Simplified Block Diagram Voltage ...
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... ISL98001CQZ-210 ISL98001CQZ-240 ISL98001CQZ-275 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . . . 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C A Recommended Operating Conditions Temperature (Commercial 0°C to +70°C Supply Voltage 3.3V, pixel rate = 140MHz for ISL98001-140, 170MHz for 25°C, unless otherwise noted A COMMENT Per Channel To achieve rated 240/275MHz speeds, see the Initialization section on page 26 ...
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... Electrical Specifications Specifications apply for V ISL98001-170, 210MHz for ISL98001-210, 240MHz for ISL98001-240, 275MHz for ISL98001-275 25MHz, T XTAL SYMBOL PARAMETER ANALOG VIDEO INPUT CHARACTERISTICS (R Input Range Input Bias Current Input Capacitance Full Power Bandwidth INPUT CHARACTERISTICS (SOG 1, SOG Input Threshold Voltage ...
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... Electrical Specifications Specifications apply for V ISL98001-170, 210MHz for ISL98001-210, 240MHz for ISL98001-240, 275MHz for ISL98001-275 25MHz, T XTAL SYMBOL PARAMETER I Analog Supply Current A I Digital Supply Current D I Crystal Oscillator Supply Current X P Total Power Dissipation D ISL98001-140 ISL98001-170 ISL98001-210 ISL98001-240 ISL98001-275 Standby Mode ...
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... [7: OUT 6 ISL98001 t t HIGH LOW SU:DAT t HD:DAT FIGURE 1. 2-WIRE INTERFACE TIMING t t HOLD SETUP The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals ...
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... The sampling phase setting determines its relative position to the rest of the AFE’s output signals IN Analog Video DATACLK [7: [7: OUT 7 ISL98001 t = 7.5ns + (PHASE/64 +8.5)*t HSYNCin-to-HSout 8.5 DATACLK Pipeline Latency Programmable Width and Polarity t = 7.5ns + (PHASE/64 +10.5)*t HSYNCin-to-HSout PIXEL ...
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... OUT FIGURE 6. 48-BIT OUTPUT MODE, INTERLEAVED TIMING 8 ISL98001 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals t = 7.5ns + (PHASE/64 +8.5)*t HSYNCin-to-HSout ...
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... Pin Configuration (MQFP, ISL98001CQZ-xxx GND BYPASS GND GND BYPASS GND RGB 1 13 GND SOG GND BYPASS GND GND ...
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... VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie unused. RESET 46 Digital input, 5V tolerant, active low, 70kΩ pullup to V the ISL98001. This pin is not necessary for normal use and may be tied directly to the V XTAL 39 Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for IN recommended loading) ...
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... Internal power for the PLL’s digital logic. Connect to VREG PLL with 0.1µF. V 52, 79, 109 Internal power for core logic. Connect to VREG CORE Reserved. Do not connect anything to these pins. 11 ISL98001 DESCRIPTION . This signal is usually not needed. OUT . IN and BYPASS , V ...
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... The minimum recommended SOG Slicer setting is 3 (60mV). 12 ISL98001 BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial silicon second revision, etc. 7:4 Device ISL98001 0 HSYNC1 Active 0: HSYNC1 is Inactive 1: HSYNC1 is Active 1 HSYNC2 Active 0: HSYNC2 is Inactive 1: HSYNC2 is Active 2 VSYNC1 Active 0: VSYNC1 is Inactive ...
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... REGISTER (DEFAULT VALUE) 0x05 Input configuration (0x00) 0x06 Red Gain (0x55) 0x07 Green Gain (0x55) 0x08 Blue Gain (0x55) 13 ISL98001 BIT(S) FUNCTION NAME 0 Channel Select 0: VGA1 1: VGA2 1 Input Coupling 0: AC coupled (positive input connected to clamp DAC during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DAC) ...
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... PLL Sampling Phase (0x00) 0x11 PLL Pre-coast (0x04) 0x12 PLL Post-coast (0x04) 14 ISL98001 BIT(S) FUNCTION NAME 7:0 Red Offset ABLC™ enabled: digital offset control. A 1LSB change in this register will shift the ADC output by 1 LSB. ABLC™ disabled: analog offset control. These bits go to the upper 8-bits of the 10-bit offset DAC ...
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... DC restore (if enabled) - start the ABLC™ function (if enabled), and - update the data to the Offset DACs (always). In the default internal CLAMP mode, the ISL98001 automatically generates the CLAMP pulse. If External CLAMP is selected, the Offset DAC values only change on the leading edge of CLAMP. If there is no ...
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... HS Width (0x10) OUT 0x1A Output Signal Disable (0x00) 0x1B Power Control (0x00) 0x1C PLL Tuning (0x49) 16 ISL98001 BIT(S) FUNCTION NAME 0 Bus Width 0: 24-bits: Data output on R are all driven low (default). 1: 48-bits: Data output Interleaving 0: No interleaving: data changes on same edge of (48-bit mode only) DATACLK (default) ...
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... Green ABLC Target (0x00) 0x1F Blue ABLC Target (0x00) 0x23 DC Restore Clamp (0x18) 17 ISL98001 BIT(S) FUNCTION NAME 7:0 Red ABLC Target This is a 2's complement number controlling the target code of the Red ADC output when ABLC is enabled. In RGB mode, the Red ADC output will be servoed to 0x00 + the number in this register (-0x00 to +0x7F) ...
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... So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The ISL98001's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point ...
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... The range for each color is typically 0V to 0.7V from black to white. HSYNC and VSYNC are separate signals. Component YPbPr Inputs In addition to RGB and RGB with SOG, the ISL98001 has an option that is compatible with the component YPbPr video inputs typically generated by DVD players. While the ISL98001 digitizes signals in these color spaces, it does not perform color space conversion ...
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... VGA1 IN R(GB) 1 GND PGA R(GB VGA2 R(GB) 2 GND The ISL98001 can optionally decimate the incoming data to provide a 4:2:2 output stream (configuration register 0x18[ shown in Table 2. TABLE 2. YUV MAPPING (4:2:2) ISL98001 ISL98001 INPUT INPUT OUTPUT SIGNAL CHANNEL ASSIGNMENT Y Green Green Pb Blue Blue Pr ...
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... SYNC Processing The ISL98001 can process sync signals from 3 different sources: discrete HSYNC and VSYNC, composite sync on the HSYNC input, or composite sync from a Sync-On-Green (SOG) signal embedded on the Green video input. The ISL98001 has SYNC activity detect functions to help the firmware determine which sync source is available ...
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... Because a phase setting this high will slightly increase jitter, the default setting (0x49) for register 0x1C is recommended for all other sync sources. PGA The ISL98001’s Programmable Gain Amplifier (PGA) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is: V GainCode ...
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... Sampling Phase The ISL98001 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. The sampling phase register is 0x10. HSYNC Slicer ...
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... SOG slicer levels and not be easily detected consequence, not all of the activity detect bits in the ISL98001 are correct under all conditions. Table 7 shows how to use the SYNC Status register (0x01) to identify the presence of and type of a sync source. The ...
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... HSYNC, which indicates a VSYNC signal. The CSYNC Present bit should be used to confirm that the signal being received is a reliable composite sync source. SYNC Output Signals The ISL98001 has 2 pairs of HSYNC and VSYNC output signals, HSYNC and VSYNC , and HS OUT ...
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... Equation 1 in the Initialization section on page 26. Standby Mode The ISL98001 can be placed into a low power standby mode by writing a 0x0F to register 0x1B, powering down the triple ADCs, the DPLL, and most of the internal clocks. ...
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... The ISL98001 has a 7-bit address on the serial bus. The upper 6-bits are permanently set to 100110, with the lower bit determined by the state of pin 48. This allows two ISL98001s to be independently controlled while sharing the same bus ...
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... FIGURE 9. VALID START AND STOP CONDITIONS SCL from Host 1 Data Output from Transmitter Data Output from Receiver Start FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER SCL SDA Data Stable FIGURE 11. VALID DATA CHANGES ON THE SDA BUS 28 ISL98001 Stop 8 Acknowledge Data Change Data Stable 9 FN6148.3 March 8, 2006 ...
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... FIGURE 12. CONFIGURATION REGISTER WRITE 29 ISL98001 Signals the beginning of serial I/O R/W ISL98001 Serial Bus Address Write This is the 7-bit address of the ISL98001 on the 2-wire bus. The A address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. Shift this 0 0 (pin 48) value left to when adding the R/W bit. ...
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... This sets the initial address of the ISL98001’s configuration register for subsequent reading. Ends the previous transaction and starts a new one R/W ISL98001 Serial Bus Address Write This is the 7-bit address of the ISL98001 on the 2-wire bus. The A address is 0x4C if pin 48 is low, 0x4D if pin 48 is high. R ...
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Metric Quad Flat Pack (MQFP) Package All dimensions in mm. ...