S80C186EC20 Intel, S80C186EC20 Datasheet - Page 29

• Manufacturer Part Number: S80C186EC20
• Description: 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
• Manufacturer: Intel

I
The I
two components
1 I
2 I
Where
Measuring C
would be difficult Instead C
the above formula with I
known V
user can calculate I
within the specified operating range
Example Calculate typical I
NOTES
1 Maximum C
(or Idle Mode) Due to tester limitations CLKOUT and OSCOUT also have 50 pF loads that increase I
2 Typical C
CC
I
V
C
f
CC
nal device leakage Measured with all inputs at
either V
discharge internal parasitic capacitance when
changing logic levels I
frequency of operation and the device supply
voltage (V
PD
CCS
DEV
e
e
CPD
CPD (Idle Mode)
versus Frequency and Voltage
CC
e
e
e
Operating Frequency
Parameter
Supply Voltage (V
consumed by the processor is composed of
I
0 1 mA
56 2 mA
The quiescent current that represents inter-
CC
e
PD
The switching current used to charge and
PD
CC
Device Capacitance
Power
and frequency Using the C
a
PD
CC
PD
is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode)
or ground and no clock applied
I
CCS
a
is measured at
) I
on a device like the 80C186EC
5 2V
e
I
CCS
CCS
CC
V
e
at any voltage and frequency
is given by the formula
I
0 77
V
e
CC
CCS
CC
CC
V
)
C
b
2
PD
DEV
14 MHz
is related to both the
40 C with all outputs loaded as specified in the AC test conditions and the device in reset
values measured at
at 14 MHz 5 2V V
C
is calculated using
DEV
Typical
f
0 77
0 55
PD
f
value the
CC
PDTMR Pin Delay Calculation
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized
To calculate the value of capacitor to use to provide
a desired delay use the equation
Where
t
C
Example For a delay of 300 s a capacitor value of
C
Round up to a standard (available) capacitor value
The above equation applies to delay time longer
than 10
tance needed to achieve the desired delay A delay
variance of
temperature
tremes In general higher V
peratures will decrease delay time while lower V
and or higher temperature will increase delay time
e
PD
PD
Max
1 37
0 96
440
desired delay in seconds
e
e
c
440
capacitive load on PDTMR in microfarads
80C186EC 188EC 80L186EC 188EC
t
e
s and will compute the TYPICAL capaci-
c
C
a
PD
(300
voltage
50% to
(5V 25 C)
mA V MHz
mA V MHz
c
Units
10
NOTE
NOTE
and device process ex-
b
b
6
25% can occur due to
e
CC
0 132 F is required
CC
and or lower tem-
by V C F
Notes
1 2
1 2
CC
29