S80C186EC20 Intel, S80C186EC20 Datasheet - Page 35

• Manufacturer Part Number: S80C186EC20
• Description: 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
• Manufacturer: Intel

AC Characteristics 80L186EC16
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at V
3 Only required to guarantee I
4 Specified for a 50 pF load see Figure 14 for capacitive derating information
5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF
6 See Figure 15 for rise and fall times
7 T
8 T
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
Relative Timings (80C186EC-25 20 13 80L186EC-16 13)
Symbol
RELATIVE TIMINGS
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
CHOV1
CHOV2
LHLL
AVLL
PLLL
LLAX
LLWL
LLRL
WHLH
AFRL
RLRH
WLWH
RHAX
WHDX
WHPH
RHPH
PHPL
OVRH
RHOX
IHIL
ILIH
CVIL
ILCX
IRES
IRLH
IRHIF
applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
applies to RD and WR only after a HOLD release
IH
for high time V
ALE Active Pulse Width
AD Valid Setup before ALE Falls
Chip Select Valid before ALE Falls
AD Hold after ALE Falls
ALE Falling to WR Falling
ALE Falling to RD Falling
WR Rising to Next ALE Rising
AD Float to RD Falling
RD Active Pulse Width
WR Active Pulse Width
RD Rising to Next Address Active
Output Data Hold after WR Rising
WR Rise to Chip Select Rise
RD Rise to Chip Select Rise
Chip Select Inactive to Next Chip
Select Active
ONCE Active Setup to RESIN Rising
ONCE Hold after RESIN Rise
INTA High to Next INTA Low
during INTA Cycle
INTA Active Pulse Width
CAS2 0 Setup before 2nd INTA
Pulse Low
CAS2 0 Hold after 2nd INTA Pulse Low
Interrupt Resolution Time
IR Low Time to Reset Edge Detector
IR Hold Time after 1st INTA Falling
CC
IL
Maximum limits are bounded by T
Parameter
for low time
(Continued)
C
T
T
2T
2T
T
T
4T
2T
CH
T
T
T
T
T
T
T
T
T
Min
b
b
b
80C186EC 188EC 80L186EC 188EC
8T
4T
50
25
0
T
T
b
b
b
b
b
b
b
b
b
and T
b
b
b
b
15
15
15
10
10
10
15
15
10
10
10
10
5
5
5
5
CL
Max
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2 4
2 4
2 4
4 5
1
1
1
1
2
2
1
1
1
4
3
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