BUL45_06 ON Semiconductor, BUL45_06 Datasheet - Page 5

• Manufacturer Part Number: BUL45_06
• Description: NPN Silicon Power Transistor
• Manufacturer: ON Semiconductor

0.01
150
140
130
120
100
100
110
1.0
0.1
1.0
0.8
0.6
0.4
0.2
90
80
70
10
0
10
20
3
DC (BUL45)
Figure 15. Forward Bias Safe Operating Area
4
Figure 17. Forward Bias Power Derating
Figure 13. Inductive Fall Time, t
40
V
5 ms
I
5
CE
C
= 2 A
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
6
T
60
C
, CASE TEMPERATURE (°C)
7
THERMAL DERATING
1 ms
h
FE
, FORCED GAIN
8
80
GUARANTEED SAFE OPERATING AREA INFORMATION
100
9
T
T
100
J
J
10
= 25°C
= 125°C
TYPICAL SWITCHING CHARACTERISTICS
50 ms
I
SECOND BREAKDOWN
C
= 1 A
11
120
DERATING
12
10 ms
fi
(I
I
V
V
L
(h
B(off)
C
CC
Z
B2
13
= 300 V
= 200 mH
FE
140
EXTENDED
= 15 V
= I
= I
)
http://onsemi.com
SOA
1 ms
C
14
/2
C
/2 for all switching)
1000
160
15
BUL45
5
transistor: average junction temperature and second breakdown.
Safe operating area curves indicate I
that must be observed for reliable operation; i.e., the transistor
must not be subjected to greater dissipation than the curves
indicate. The data of Figure 15 is based on T
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated when
T
as thermal limitations. Allowable current at the voltages shown in
Figure 15 may be found at any case temperature by using the
appropriate curve on Figure 17. T
data in Figures 20. At any case temperatures, thermal limitations
will reduce the power that can be handled to values less than the
limitations imposed by second breakdown. For inductive loads,
high voltage and current must be sustained simultaneously during
turn−off with the base−to−emitter junction reverse−biased. The
safe level is specified as a reverse−biased safe operating area
(Figure 16). This rating is verified under clamped conditions so
that the device is never subjected to an avalanche mode.
Figure 16. Reverse Bias Switching Safe Operating Area
C
300
250
200
150
100
There are two limitations on the power handling ability of a
50
≥ 25°C. Second breakdown limitations do not derate the same
6
5
4
3
2
1
0
300
3
4
V
CE
5
V
400
T
T
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
BE(off)
J
J
= 25°C
= 125°C
Figure 14. Crossover Time
6
= 0 V
7
h
FE
500
, FORCED GAIN
8
I
C
= 2 A
−1.5 V
J(pk)
9
C
− V
may be calculated from the
10
I
600
C
CE
= 1 A
11
limits of the transistor
C
−5 V
12
= 25°C; T
T
I
L
C
700
C
C
V
V
I
L
/I
B(off)
C
CC
Z
B
= 500 mH
≤ 125°C
13
= 200 mH
= 300 V
≥ 4
= 15 V
= I
C
14
/2
J(pk)
800
15
is