LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 148

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

General-Purpose Timers
148
Reset
Reset
Type
Type
Bit/Field
31:4
GPTM TimerA Mode (GPTMTAMR)
Offset 0x004
1:0
3
2
RO
RO
31
15
0
0
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
RO
RO
30
14
0
0
reserved
TACMR
TAAMS
TAMR
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerA Alternate Mode Select
0: Capture mode is enabled.
1: PWM mode is enabled.
Note:
GPTM TimerA Capture Mode
0: Edge-Count mode.
1: Edge-Time mode.
GPTM TimerA Mode
0x0: Reserved.
0x1: One-Shot Timer mode.
0x2: Periodic Timer mode.
0x3: Capture mode.
The Timer mode is based on the timer configuration defined by
bits 2:0 in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer
modes for TimerA.
In 32-bit timer configuration, this register controls the mode and
the contents of GPTMTBMR are ignored.
RO
RO
24
0
8
0
reserved
To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TAAMS TACMR
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 5, 2006
R/W
RO
17
0
1
0
TAMR
R/W
RO
16
0
0
0