LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 80

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
80
Reset
Reset
Type
Type
Bit/Field
31:1
Deep-Sleep Clock Configuration (DSLPCLKCFG)
Offset 0x144
0
RO
RO
31
15
0
0
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register is used to automatically switch from the main oscillator to the internal oscillator when
entering Deep-Sleep mode. The system clock source is the main oscillator by default. When this
register is set, the internal oscillator is powered up and the main oscillator is powered down. When
the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and
frequency it had at the onset of Deep-Sleep mode.
RO
RO
30
14
0
0
Reserved
Name
IOSC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
This field allows an override of the main oscillator when
Deep-Sleep mode is running. When set, this field forces the
internal oscillator to be the clock source during Deep-Sleep
mode. Otherwise, the main oscillator remains as the default
system clock source.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
October 5, 2006
RO
RO
17
0
1
0
IOSC
R/W
RO
16
0
0
0