LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 245

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

October 5, 2006
Reset
Reset
Type
Type
Bit/Field
SSI Interrupt Mask (SSIIM)
Offset 0x014
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the
corresponding mask.
RO
RO
30
14
0
0
reserved
RORIM
Name
RXIM
TXIM
RTIM
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
R/W
R/W
R/W
R/W
27
11
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
0
0
0
0
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI Transmit FIFO Interrupt Mask
0: TX FIFO half-full or less condition interrupt is masked.
1: TX FIFO half-full or less condition interrupt is not masked.
SSI Receive FIFO Interrupt Mask
0: RX FIFO half-full or more condition interrupt is masked.
1: RX FIFO half-full or more condition interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
0: RX FIFO time-out interrupt is masked.
1: RX FIFO time-out interrupt is not masked.
SSI Receive Overrun Interrupt Mask
0: RX FIFO overrun interrupt is masked.
1: RX FIFO overrun interrupt is not masked.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TXIM
R/W
RO
19
0
3
0
RXIM
LM3S101 Data Sheet
R/W
RO
18
0
2
0
RTIM
R/W
RO
17
0
1
0
RORIM
R/W
RO
16
0
0
0
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