LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 92

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Internal Memory
92
Reset
Reset
Type
Type
Bit/Field
31:16
15:4
Flash Memory Control (FMC)
Offset 0x008
3
2
WO
RO
31
15
0
0
Register 6: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the
location specified by the Flash Memory Address (FMA) register (see page 90). If the access is a
write access, the data contained in the Flash Memory Data (FMD) register (see page 91) is
written.
This is the final register written and initiates the memory operation. There are four control bits in
the lower byte of this register that, when set, initiate the memory operation. The most used of
these register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
WO
RO
30
14
0
0
MERASE
reserved
WRKEY
COMT
Name
WO
RO
29
13
0
0
WO
RO
28
12
0
0
Type
R/W
R/W
WO
RO
WO
RO
27
11
0
0
RO
WO
26
10
0
0
reserved
Reset
0x0
RO
WO
25
0
9
0
0
0
0
Preliminary
RO
WO
24
0
8
0
WRKEY
Description
This field contains a write key, which is used to minimize the
incidence of accidental flash writes. The value 0xA442 must
be written into this field for a write to occur. Writes to the
FMC register without this WRKEY value are ignored. A
read of this field returns the value 0.
Reserved bits return an indeterminate value, and should
never be changed.
Commit (write) of register value to nonvolatile storage. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous commit access is provided.
If the previous commit access is complete, a 0 is returned;
otherwise, if the commit access is not complete, a 1 is
returned.
This can take up to 50 μs.
Mass erase flash memory
If this bit is set, the flash main memory of the device is all
erased. A write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is
provided. If the previous mass erase access is complete, a
0 is returned; otherwise, if the previous mass erase access
is not complete, a 1 is returned.
This can take up to 250 ms.
WO
RO
23
0
7
0
WO
RO
22
0
6
0
WO
RO
21
0
5
0
WO
RO
20
0
4
0
COMT
R/W
WO
19
0
3
0
MERASE ERASE WRITE
R/W
WO
18
0
2
0
October 5, 2006
R/W
WO
17
0
1
0
R/W
WO
16
0
0
0