LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 38

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

JTAG Interface
5.2.1.4
5.2.1.5
5.2.2
38
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the
pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains
enabled on PC1/TMS; otherwise JTAG communication could be lost.
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the
pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains
enabled on PC2/TDI; otherwise JTAG communication could be lost.
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is
placed in an inactive drive state when not actively shifting out data. Because TDO can be
connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard
1149.1 expects the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up
and pull-down resistors can be turned off to save internal power if a High-Z output value is
acceptable during certain TAP controller states.
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 39. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state,
please refer to IEEE Standard 1149.1.
Preliminary
October 5, 2006