LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 172

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Watchdog Timer
172
Reset
Type
Reset
Type
Bit/Field
31:2
Watchdog Control (WDTCTL)
Offset 0x008
1
0
RO
RO
31
15
0
0
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (upon second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
RO
RO
30
14
0
0
reserved
RESEN
INTEN
Name
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Watchdog Reset Enable
0: Disabled.
1: Enable the Watchdog module reset output.
Watchdog Interrupt Enable
0: Interrupt event disabled (once this bit is set, it can only
be cleared by a hardware reset)
1: Interrupt event enabled. Once enabled, all writes are
ignored.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
October 5, 2006
RESEN
R/W
RO
17
0
1
0
INTEN
R/W
RO
16
0
0
0