CY28404 Cypress Semiconductor, CY28404 Datasheet
CY28404
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CY28404 Summary of contents
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... SCLK* PCI4 18 31 3V66_0 PCI5 19 30 3V66_1 20 29 VSS_3V66 21 28 VDD_3V66 DOT_48 22 27 3V66_2/MODE* USB_48 23 26 3V66_3/VCH/SELVCH** VSS_48 24 25 VDD_48 SSOP-48 * 150k Internal Pull-up ** 150k Internal Pull-down *** Do Not Connect , • San Jose CA 95134 • 408-943-2600 Revised June 16, 2004 CY28404 48M x 3 ...
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... MHz MHz I 3.3V LVTTL Input is a Level Sensitive Strobe used to Latch the FS[A:E] Input (active LOW). I/O SMBus-compatible SDATA. I SMBus-compatible SCLOCK. PWR 3.3V Power Supply for PLL. GND Ground for PLL. PWR 3.3V Power Supply for Outputs. GND Ground for Outputs. CY28404 Description Page ...
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... Reserved Reserved 0 0 100.0 66 133.3 66 200.0 66 Reserved Reserved CY28404 PLL Gear Constants PCI VCO Freq. (G) 33.6 805.6 24004009.32 33.4 801.6 24004009.32 36.0 864.0 24004009.32 33.7 809.6 24004009.32 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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... Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop CY28404 2 C Page ...
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... Reserved, set = 1 Reserved, set = 1 Reserved, set = 1 Reserved, set = 1 CPU(T/C)1 Output Enable Disabled (three-state Enabled CPU(T/C)0 Output Enable 0 = Disabled (three-state Enabled CY28404 Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation, bits[6:0] ...
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... Allow control of PCIF1 with assertion of SW PCI_STP 0 = Free Running Stopped with SW PCI_STP Allow control of PCIF0 with assertion of SW PCI_STP 0 = Free Running Stopped with SW PCI_STP PCIF2 Output Enable 0 = Disabled Enabled PCIF1 Output Enable 0 = Disabled Enabled PCIF0 Output Enable 0 = Disabled Enabled CY28404 Description Description Description Page ...
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... Reserved, set = 0 Spread Spectrum Enable 0 = Spread Off Spread On REF_1 Output Enable 0 = Disabled Enabled REF_0 Output Enable 0 = Disabled Enabled Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28404 Description Description Description Page ...
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... REF_2 Output Enable0 = Disabled Enabled) Reserved, set = 0 Reserved, set = 0 Name PCI skew control 00 = Normal 01 = –500 Reserved 11 = +500 ps 3V66 skew control 00 = Normal 01 = –150 +150 +300 ps Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 CY28404 Description Description Description Page ...
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... When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Name FS_Override 0 = Select operating frequency by FS(E:A) input pins 1 = Select operating frequency by FSEL(4:0) settings Reserved, set = 0 Reserved, set = 0 CY28404 Description Description Description Description Page ...
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... Crystal Recommendations The CY28404 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28404 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... There exists an I2C bit that allows for the CPUT/C outputs to be three-stated during power-down. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. CY28404 Pin Cs2 Trace 2 ...
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... CPUT/C outputs must be driven to greater than 200 mV is less than 300 µs. PWRDWN# CPUT, 133MHz CPUC, 133MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.131818 Figure 4. Power-down Deassertion Timing Waveforms Document #: 38-07510 Rev. *B Tstable <1.8ms Tdrive_PWRDN# <300µs, >200mV CY28404 Page ...
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... If the Watchdog times out before the new SMBus reprograms the Watchdog Timer bits to (0000), then this device will send a low system reset pulse, on SRESET# and changes WD Time-out bit to “1”. CY28404 Device is not affected, VTT_PWRGD# is ignored State 3 On ...
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... YES Frequency Revert Bit = 0 Frequency Revert Bit = 1 Set Frequency to Set Frequency to FS_HW_Latched FS_SW Setting SRESET for 3 msec Reset & Revert Frequency back CY28404 FREQUENCY Set Pro_Freq_EN = 1 Set WD Timer Bits to Extend Time YES NO System need Extend Time for next count NO CLEAR W D TIMER ...
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... At 1/8 in. Conditions 3.3V ± 5% SDATA, SCLK SDATA, SCLK V Except Pull-ups or Pull-downs 0 < V < – 200-MHz and all outputs loaded per Table 10 and Figure 8 PD# Asserted CY28404 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 +150 ° ° ...
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... Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V, High drive Measurement at 0.4V, High drive Measured between 0.4V and 2.4V, High drive Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V, High drive Measurement at 0.4V, High drive Measured between 0.4V and 2.4V, High drive Measurement at 1.5V CY28404 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps 300 ppm ...
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... Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Conditions Min. 1.5 ns Typical 0° 180° 0° Max Load CY28404 Min. Max. – 400 45 55 20.8271 20.8396 8.806 10.486 8.794 10.386 0.5 1.0 – 350 – 500 45 55 20.8271 20 ...
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... Output Current REF I = 6*I OH REF Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C CY28404 0. Page ...
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... Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 48-lead Shrunk Small Outline Package O48 2 C system, provided that the system conforms to the I CY28404 51-85061-* Standard Specification ...
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... Document History Page Document Title: CY28404 CK409-Compliant Clock Synthesizer Document Number: 38-07510 Issue REV. ECN NO. Date ** 125355 04/14/03 *A 127160 06/16/03 *B 235908 See ECN Document #: 38-07510 Rev. *B Orig. of Change RGL New Data Sheet RGL Removed the SRC functionality Modified the title to CK409-Compliant Clock Synthesizer ...