CY28404 Cypress Semiconductor, CY28404 Datasheet - Page 3

• Manufacturer Part Number: CY28404
• Description: CK409-COMPLIANT CLOCK SYNTHESIZER
• Manufacturer: Cypress Semiconductor

Document #: 38-07510 Rev. *B
MODE Select
The hardware strapping MODE input pin can be used to select
the functionality of the RESET#/PD# pin. The default (internal
pull-up) configuration is for this pin to function as a RESET#
Watchdog output. When pulled LOW during device Power-up,
the RESET#/PD# pin will be configured to function as a
Power-down input pin.
Table 2. Frequency Selection Table
FSEL_4
FS_E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FSEL_3
FS_D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input Conditions
FSEL_2
FS_C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSEL_1
FS_B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSEL_0
FS_A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
100.7
100.2
108.0
101.2
125.7
130.3
133.6
134.2
134.5
148.0
167.4
170.0
175.0
180.0
185.0
190.0
100.9
133.9
200.9
100.0
133.3
200.0
CPU
Output Frequency
Frequency Select Pins
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A through FS_E inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A through FS_E input values. For all logic
levels of FS_A through FS_E VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#
and FS_A through FS_E transitions will be ignored.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3V66
67.1
66.8
72.0
67.5
62.9
65.1
66.8
67.1
67.3
74.0
55.8
56.7
58.3
60.0
61.7
63.3
67.3
67.0
67.0
66.7
66.7
66.7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
33.6
33.4
36.0
33.7
31.4
32.6
33.4
33.6
33.6
37.0
27.9
28.3
29.2
30.0
30.8
31.7
33.6
33.5
33.5
33.3
33.3
33.3
PCI
VCO Freq.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
805.6
801.6
864.0
809.6
754.2
781.6
801.6
805.2
807.0
888.0
669.6
680.0
700.0
720.0
740.0
760.0
807.2
803.4
803.6
800.0
800.0
800.0
CY28404
24004009.32
24004009.32
24004009.32
24004009.32
32005345.76
32005345.76
32005345.76
32005345.76
32005345.76
32005345.76
48008018.65
48008018.65
48008018.65
48008018.65
48008018.65
48008018.65
24004009.32
32005345.76
48008018.65
24004009.32
32005345.76
48008018.65
Constants
PLL Gear
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Page 3 of 20
(G)