CY28404 Cypress Semiconductor, CY28404 Datasheet - Page 11

• Manufacturer Part Number: CY28404
• Description: CK409-COMPLIANT CLOCK SYNTHESIZER
• Manufacturer: Cypress Semiconductor

Document #: 38-07510 Rev. *B
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(C
series with the crystal, trim capacitors (CE1,CE2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (C
the crystal is in series with the crystal, trim capac-
itors(CE1,CE2) should be calculated to provide equal capaci-
tative loading on both sides.
L
). While the capacitance on each side of the crystal is in
L
). While the capacitance on each side of
Cs1
Figure 2. Crystal Loading Example
Ce1
X1
Ci1
Clock Chip
XTAL
Ci2
Use the following formulas to calculate the trim capacitor
values for CE1 and CE2.
PD# (Power-down) Clarification
The PD# pin is used to shut off all clocks and PLLs without
having to remove power from the device. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the power down state.
PD# – Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPUT) clocks
must be held LOW on their next HIGH to LOW transition. CPU
clocks must be held with CPUT clock pin driven HIGH with a
value of 2x Iref and CPUC undriven as the default condition.
There exists an I2C bit that allows for the CPUT/C outputs to
be three-stated during power-down. Due to the state of internal
logic, stopping and holding the REF clock outputs in the LOW
state may require more than one clock cycle to complete.
X2
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
Ce .....................................................External trim capacitors
Cs.............................................Stray capacitance (trace,etc.)
Ci ............ Internal capacitance (lead frame, bond wires etc.)
......................................using standard value trim capacitors
Ce2
CLe
Total Capacitance (as seen by the crystal)
=
Cs2
(
3 to 6p
Load Capacitance (each side)
33pF
Ce1 + Cs1 + Ci1
Pin
Trim
Trace
2.8pF
Ce = 2 * CL – (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
CY28404
Page 11 of 20
)