CY28410-2 Cypress Semiconductor, CY28410-2 Datasheet
CY28410-2
Related parts for CY28410-2
CY28410-2 Summary of contents
Page 1
... VTT_PWRGD#/PD DOT96T DOT96C FS_A USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4-SATAT SRC4_SATAC VDD_SRC • 3901 North First Street • San Jose www.DataSheet4U.com CY28410-2 Grantsdale Chipset PCI REF DOT96 USB_48 PCI2 2 55 PCI1 3 54 PCI0 4 ...
Page 2
... LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for asserting power-down (active HIGH) I 14.318-MHz Crystal Input O, SE 14.318-MHz Crystal Output CY28410-2 www.DataSheet4U.com Description ,V ,V ILFS_C IMFS_C ...
Page 3
... Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeat start 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 Byte Count from slave – 8 bits 38 Acknowledge CY28410-2 www.DataSheet4U.com DOT96 USB 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz Hi-Z Hi-Z REF REF REF ...
Page 4
... Disable (Hi-Z Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z Enable Reserved, Set = 1 CY28410-2 www.DataSheet4U.com Block Read Protocol Description Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave – ...
Page 5
... Allow control of SRC[T/C]5 with assertion of SW PCI_STP Free running Stopped with SW PCI_STP# SRC4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP Free running Stopped with SW PCI_STP# SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP Free running Stopped with SW PCI_STP# CY28410-2 www.DataSheet4U.com Description Description Description Page ...
Page 6
... Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted Name REF/N or Hi-Z Select 1 = REF/N Clock Hi-Z Test Clock Mode Entry Control 1 = REF/N or Hi-Z mode Normal operation Reserved, Set = 0 REF REF Output Drive Strength 0 = Low High CY28410-2 www.DataSheet4U.com Description Description Description Description Page ...
Page 7
... Crystal Recommendations The CY28410-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28410-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
Page 8
... HIGH in less than 300 µ deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles CY28410-2 www.DataSheet4U.com Page ...
Page 9
... PCI, 33 MHz REF PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF Figure 4. Power-down Deassertion Timing Waveform Document #: 38-07747 Rev *.* Figure 3. Power-down Assertion Timing Waveform Tstable <1.8nS Tdrive_PW RDN# <300µS, >200mV CY28410-2 www.DataSheet4U.com Page ...
Page 10
... VD D_A = off O peration VTT_PW toggle Condition Relative Non-functional Functional Functional SSOP TSSOP SSOP TSSOP MIL-STD-883, Method 3015 At 1/8 in. CY28410-2 www.DataSheet4U.com Device is not affected, VTT_PW RGD# is ignored State ple Inputs straps W ait for <1.8m s Enable O utputs Min. Max. Unit –0.5 4 ...
Page 11
... When XIN is driven from an external clock source Measured between 0.3V and 0. average over 1-µs duration Over 150 ms Measured at crossing point V OX Measured at crossing point V OX CY28410-2 www.DataSheet4U.com Min. Max. Unit 3.135 3.465 – 1.0 2.2 – V – 0.3 ...
Page 12
... Determined as a fraction of 2*(T – T )/( Math averages Figure 7 Math averages Figure 7 See Figure 7. Measure SE Measured at crossing point V Measured at crossing point V Measured at crossing point V CY28410-2 www.DataSheet4U.com Min. 7.497751 7.502251 OX 4.998500 5.001500 OX 3.748875 3.751125 OX 9.997001 10.05327 OX 7.497751 7.539950 OX 4.998500 5.026634 OX 3.748875 3.769975 OX 9 ...
Page 13
... Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 7 CY28410-2 www.DataSheet4U.com Min. 10.12800 9.872001 OX 9.872001 10.17827 OX – OX – OX – 0.175 to 175 – ) – – ...
Page 14
... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1. Ω Ω D iff tia Ω Ω Figure 7. 0.7V Single-ended Load Configuration CY28410-2 www.DataSheet4U.com Min. Max. –150 – 250 550 – V HIGH 0.3 –0.3 – ...
Page 15
... Figure 8. Single-ended Load Configuration Package Type CY28410-2 www.DataSheet4U.com Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF - Product Flow Commercial, 0 ° ...
Page 16
... SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28410-2 www.DataSheet4U.com 51-85062-*C DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. ...
Page 17
... Document History Page Document Title: CY28410-2 Clock Generator for Intel Document Number: 38-07747 REV. ECN NO. Issue Date ** 331162 See ECN Document #: 38-07747 Rev *.* Grantsdale Chipset Orig. of Change Description of Change RGL New Data Sheet CY28410-2 www.DataSheet4U.com Page ...