CY28410-2 Cypress Semiconductor, CY28410-2 Datasheet - Page 2

• Manufacturer Part Number: CY28410-2
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07747 Rev *.*
Pin Definitions
44,43,41,40
36,35
14,15
18
16
53
39
54,55,56,3,4,5 PCI
9,10
8
52
46
47
26,27
19,20,22,23,2
4,25,31,30,33,
32
12
11
42
1,7
48
21,28,34
37
13
45
2,6
51
29
38
17
50
49
Pin No.
CPUT/C
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
DOT96T, DOT96C
FS_A
FS_B/TEST_MODE
FS_C/TEST_SEL
IREF
PCIF
PCIF0/ITP_EN
REF
SCLK
SDATA
SRC4_SATAT,
SRC4_SATAC
SRCT/C
USB_48
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
XIN
XOUT
Name
I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
I/O, SE Fixed 48 MHz clock output.
O, DIF Differential CPU clock outputs.
O, DIF Selectable Differential CPU or SRC clock output.
O, DIF Fixed 96-MHz clock output.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Differential serial reference clocks.
O, SE 33-MHz clocks.
O, SE 33-MHz clocks.
O, SE Reference clock. 3.3V 14.318-MHz clock output.
O, SE 14.318-MHz Crystal Output
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
GND
GND
GND
GND
GND
GND
I, PU
Type
I/O
I
I
I
I
I
I
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
3.3V tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z,1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V tolerant input for CPU frequency selection. Selects test mode if pulled
to V
Refer to DC Electrical Specifications table for V
cations.
A Precision resistor is attached to this pin, which is connected to the internal
current reference.
1 = CPU2_ITP, 0 = SRC7
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for PLL.
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active LOW) assertion, this pin becomes a realtime input for asserting
power-down (active HIGH)
14.318-MHz Crystal Input
IHFS_C
when VTT_PWRGD# is asserted LOW.
Description
ILFS_C
,V
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IMFS_C
CY28410-2
,V
IHFS_C
Page 2 of 17
specifi-