CY28410-2 Cypress Semiconductor, CY28410-2 Datasheet - Page 7

• Manufacturer Part Number: CY28410-2
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07747 Rev *.*
Byte 6: Control Register 6 (continued)
Byte 7: Vendor ID
Crystal Recommendations
The CY28410-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28410-2 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Table 5. Crystal Recommendations
14.31818 MHz
Frequency
Bit
Bit
1
3
2
0
7
6
5
4
3
2
1
0
(Fund)
Externally
Externally
Externally
selected
selected
selected
@Pup
@Pup
1
0
0
1
0
1
0
0
0
Cut
AT
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Loading Load Cap
Parallel
PCIF, SRC, PCI
CPUT/C
CPUT/C
CPUT/C
Name
Name
20 pF
0.1 mW
(max.)
SW PCI_STP# Function
Drive
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FS_C. Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B. Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A. Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Shunt Cap
(max.)
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
5 pF
Figure 1. Crystal Capacitive Clarification
Motional
0.016 pF
(max.)
Description
Description
Tolerance
35 ppm
(max.)
www.DataSheet4U.com
Stability
30 ppm
(max.)
CY28410-2
Page 7 of 17
(max.)
Aging
5 ppm