IDT72805LB15PFI8 IDT, Integrated Device Technology Inc, IDT72805LB15PFI8 Datasheet - Page 13

• Manufacturer Part Number: IDT72805LB15PFI8
• Description: IC FIFO SYNC DUAL 256X18 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72805LB15PFI8

• Function: Synchronous
• Memory Size: 4.6K (256 x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72805LB15PFI8

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. When t
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
Q
D
0
of WCLK and the rising edge of RCLK is less than t
0
applies only at the Empty Boundary (EF = LOW).
WCLK
0
WCLK
SKEW1
RCLK
RCLK
- Q
WEN
- D
WEN
- Q
REN
REN
OE
OE
EF
EF
17
17
17
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge
minimum specification, t
t
t
ENS
ENS
t
DS
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
FRL
t
D
OLZ
(maximum) = t
0
(first valid write)
t
ENH
t
CLKH
t
SKEW1
SKEW1
t
REF
t
CLK
A
, then EF may not change state until the next RCLK edge.
t
+ t
OE
t
SKEW1
OLZ
t
CLK
. When t
t
FRL
NO OPERATION
(1)
SKEW1
t
SKEW1
D
1
t
t
< minimum specification, t
CLKL
REF
t
(1)
ENS
13
t
OE
TM
VALID DATA
FRL
D
t
(maximum) = either 2*t
2
A
t
REF
t
OHZ
COMMERCIAL AND INDUSTRIAL
CLK
D
0
+ t
SKEW1 or
D
t
TEMPERATURE RANGES
A
3
t
CLK
+ t
JANUARY 13, 2009
SKEW1
. The Latency Timing
D
1
3139 drw 08
3139 drw 07
D
4