IDT72805LB15PFI8 IDT, Integrated Device Technology Inc, IDT72805LB15PFI8 Datasheet - Page 25

• Manufacturer Part Number: IDT72805LB15PFI8
• Description: IC FIFO SYNC DUAL 256X18 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72805LB15PFI8

• Function: Synchronous
• Memory Size: 4.6K (256 x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72805LB15PFI8

DEPTH EXPANSION CONFIGURATION (FWFT MODE)
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72805LB/72815LB/72825LB/72835LB/
72845LB devices.
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (“ripple down”) until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
PAF
HF
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
In FWFT mode, the FIFOs can be connected in series (the data outputs
Care should be taken to select FWFT mode during Master Reset for all
For an empty expansion configuration, the amount of time it takes for OR
n
(N – 1)*(4*transfer clock) + 3*T
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous
IR
Dn
WCLK
WEN
(0,1)
FL
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
72805
72815
72825
72835
72845
GND
RXI
TRANSFER CLOCK
WXI
V
CC
RCLK
REN
RCLK
OR
OE
Qn
RCLK
is the RCLK
GND
n
25
t
and transfer clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will “bubble up” from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the
t
and transfer clock, for the IR flag.
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
SKEW1
SKEW1
The “ripple down” delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the
The Transfer Clock line should be tied to either WCLK or RCLK,
TM
specification is not met between WCLK and transfer clock, or RCLK
specification is not met between RCLK and transfer clock, or WCLK
WCLK
IR
Dn
WEN
(N – 1)*(3*transfer clock) + 2 T
(0,1)
FL
72805
72815
72825
72835
72845
GND
RXI
COMMERCIAL AND INDUSTRIAL
WXI
V
TEMPERATURE RANGES
RCLK
CC
REN
OR
OE
Qn
JANUARY 13, 2009
WCLK
OUTPUT ENABLE
n
OUTPUT READY
WCLK
READ ENABLE
READ CLOCK
DATA OUT
is the WCLK
3139 drw 31
PAE
HF