IDT72805LB15PFI8 IDT, Integrated Device Technology Inc, IDT72805LB15PFI8 Datasheet - Page 8

• Manufacturer Part Number: IDT72805LB15PFI8
• Description: IC FIFO SYNC DUAL 256X18 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72805LB15PFI8

• Function: Synchronous
• Memory Size: 4.6K (256 x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72805LB15PFI8

by bringing the LD pin HIGH, the FIFO is returned to normal read/write
operation. When the LD pin and WEN are again set LOW, the next offset
register in sequence is written.
Q
read on the next LOW-to-HIGH transition of RCLK. The first transition of
RCLK will present the Empty Offset value to the data output lines. The next
transition of RCLK will present the Full offset value. Offset register content
can be read out in the IDT Standard mode only. It cannot be read in the
FWFT mode.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
ured during the "Configuration at Reset" cycle described in Table 3 with
either asynchronous or synchronous timing for PAE and PAF flags.
PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset
to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is
asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia-
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
NOTES:
1. n = Empty offset (Default Values : IDT72805LB n = 31, IDT72815LB n = 63, IDT72825LB/72835LB/72845LB n = 127)
2. m = Full Offset (Default Values : IDT72805LB m = 31, IDT72815LB m = 63, IDT72825LB/72835LB/72845LB m = 127)
NOTES:
1. n = Empty offset (Default Values : IDT72805LB n=31, IDT72815LB n = 63, IDT72825LB/72835LB/72845LB n = 127)
2. m = Full offset (Default Values : IDT72805LB m=31, IDT72815LB m = 63, IDT72825LB/72835LB/72845LB m = 127)
TABLE 2 — STATUS FLAGS FOR FWFT MODE
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
0
129 to (256-(m+1))
130 to (257-(m+1))
-Q
The contents of the offset registers can be read on the data output lines
The IDT72805LB/72815LB/72825LB/72835LB/72845LB can be config-
If asynchronous PAE/PAF configuration is selected (as per Table 3), the
(256-m) to 255
(n + 1) to 128
(n + 2) to 129
(257-m) to 256
IDT72805LB
IDT72805LB
1 to (n + 1)
11
1 to n
when the LD pin is set LOW and REN is set LOW. Data can then be
256
257
0
0
(1)
(1)
(2)
(2)
257 to (512-(m+1))
258 to (513-(m+1))
(512-m) to 511
(n + 1) to 256
(513-m) to 512
(n + 2) to 257
IDT72815LB
IDT72815LB
1 to (n + 1)
1 to n
512
513
0
0
(1)
(1)
(2)
(2)
Number of Words in FIFO
513 to (1,024-(m+1))
514 to (1,025-(m+1))
(1,024-m) to 1,023
(1,025-m) to 1,024
Number of Words in FIFO
(n + 1) to 512
IDT72825LB
(n + 2) to 513
IDT72825LB
1 to (n + 1)
1 to n
1,024
1,025
0
0
(1)
(1)
(2)
(2)
1,025 to (2,048-(m+1))
1,026 to (2,049-(m+1))
(2,048-m) to 2,047
8
(2,049-m) to 2,048
(n + 1) to 1,024
(n + 2) to 1,025
IDT72835LB
grams, see Figure 13 for asynchronous PAE timing and Figure 14 for
asynchronous PAF timing.
and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. For
detail timing diagrams, see Figure 22 for synchronous PAE timing and
Figure 23 for synchronous PAF timing.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
ured during the "Configuration at Reset" cycle described in Table 4 with
single, double or triple register-buffered flag output signals. The various
combinations available are described in Table 4 and Table 5. In general,
going from single to double or triple buffered flag outputs removes the
possibility of metastable flag indications on boundary states (i.e, empty or
full conditions). The trade-off is the addition of clock cycle delays for the
respective flag to be asserted. Not all combinations of register-buffered flag
outputs are supported. Register-buffered outputs apply to the Empty Flag
and Full Flag only. Partial flags are not effected. Table 4 and Table 5
summarize the options available.
IDT72835LB
1 to (n + 1)
1 to n
2,048
If synchronous PAE/PAF configuration is selected, the PAE is asserted
The IDT72805LB/72815LB/72825LB/72835LB/72845LB can be config-
2,049
0
0
(1)
TM
(1)
(2)
(2)
2,049 to (4,096-(m+1))
2,050 to (4,097-(m+1))
(4,096-m) to 4,095
(4,097-m) to 4,096
(n + 1) to 2,048
(n + 2) to 2,049
IDT72845LB
IDT72845LB
1 to (n + 1)
1 to n
4,096
4,097
0
0
(1)
COMMERCIAL AND INDUSTRIAL
(1)
(2)
(2)
TEMPERATURE RANGES
FF PAF
IR PAF HF PAE OR
H
H
H
H
H
H
L
L
L
L
L
L
JANUARY 13, 2009
H
H
H
H
L
L
H
H
H
H
L
L
HF
H
H
H
H
H
H
L
L
L
L
L
L
PAE EF
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L