IDT723626L15PF8 IDT, Integrated Device Technology Inc, IDT723626L15PF8 Datasheet - Page 5

• Manufacturer Part Number: IDT723626L15PF8
• Description: IC FIFO SYNC 256X36X2 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723626L15PF8

• Function: Synchronous
• Memory Size: 18.4K (256 x 36 x 2)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723626L15PF8

PIN DESCRIPTIONS (CONTINUED)
NOTE:
1. SIZEB, SIZEC and SPM are not TTL compatible. These inputs should be tied to GND or VCC.
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
FS1/SEN Flag Offset
MBA
MBB
MBC
MBF1
MBF2
MRS1
MRS2
PRS1
PRS2
RENB
SIZEB
SIZEC
SPM
WENC
W/RA
Symbol
(1)
(1)
(1)
Select 1/
Serial Enable,
Flag Offset
Select 0/
Serial Data
Port A Mailbox
Select
Port B Mailbox
Select
Port C Mailbox
Select
Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
Master Reset
Master Reset
Partial Reset
Partial Reset
Port B
Bus Size Select
Port C
Bus Size Select
Serial Programming I
Mode
Port C Write Enable
Port A Write/Read
Select
Port B Read Enable I
Name
I/O
I
I
I
I
I
I
I
I
I
I
I
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output
FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three Offset register
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load
from Port A, and serial FS0/SD load.
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 32 for the
IDT723626, 36 for the IDT723636, and 40 for the IDT723646. The first bit write stores the Y-register (Y1) MSB
and the last bit write stores the X-register (X2) LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs
are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2
output-register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Master Reset.
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or parallel)
and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and C for bus size
and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while MRS1 is LOW.
register to all zeroes. A LOW-to-HIGH transition on MRS2 toggled simultaneously with MRS1, selects the programming
method (serial or parallel) and one of the three flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA
and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement for
ports B and C. The level of SIZEB must be static throughout device operation.
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement for
ports B and C. The level of SIZEC must be static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming
or default offsets (8, 16, or 64).
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
5
Description
COMMERCIAL TEMPERATURE RANGE