IDT723626L15PF8 IDT, Integrated Device Technology Inc, IDT723626L15PF8 Datasheet

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IDT723626L15PF8

Manufacturer Part Number
IDT723626L15PF8
Description
IC FIFO SYNC 256X36X2 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723626L15PF8

Function
Synchronous
Memory Size
18.4K (256 x 36 x 2)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723626L15PF8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723626L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES:
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
©
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
EFA/ORA
FS1/SEN
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Memory storage capacity:
Clock frequencies up to 83 MHz (8ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
FFA/IRA
FS0/SD
MRS1
A
MBF2
CLKA
W/RA
PRS1
MBA
SPM
0
CSA
ENA
AEA
AFA
-A
35
IDT723626 – 256 x 36 x 2
IDT723636 – 512 x 36 x 2
IDT723646 – 1,024 x 36 x 2
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
36
36
10
CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2
FIFO1
FIFO2
Programmable Flag
Offset Registers
36
Pointer
Pointer
Read
Write
36
Status Flag
Status Flag
RAM ARRAY
1,024 x 36
RAM ARRAY
1,024 x 36
256 x 36
512 x 36
256 x 36
512 x 36
Register
Register
Mail 1
Mail 2
Logic
Logic
1
Pointer
Pointer
Timing
Read
Write
Mode
• • • • •
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• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
DESCRIPTION:
CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
36
36
The IDT723626/723636/723646 is a monolithic, high-speed, low-power,
TM
FEBRUARY 2009
(B and C)
Common
18
Control
Control
FIFO2,
Mail2
Reset
Logic
Control
Port-B
Logic
Port-C
Logic
Port
Logic
18
IDT723626
IDT723636
IDT723646
3271 drw01
MBF1
B
CLKB
CSB
MBB
SIZEB
EFB/ORB
AEB
BE
FWFT
FFC/IRC
AFC
MRS2
PRS2
C
CLKC
WENC
MBC
SIZEC
RENB
DSC-3271/5
0
0
-B
-C
17
17

Related parts for IDT723626L15PF8

IDT723626L15PF8 Summary of contents

Page 1

FEATURES: • • • • • Memory storage capacity: IDT723626 – 256 IDT723636 – 512 IDT723646 – 1,024 • • • • • Clock frequencies ...

Page 2

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 DESCRIPTION (CONTINUED) frequencies MHz and has read access times as fast as 8 ns. ...

Page 3

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 each port are independent of one another and can be asynchronous or coincident. The enables for each ...

Page 4

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. ...

Page 5

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O FS1/SEN Flag Offset I FS1/SEN and FS0/SD are dual-purpose inputs used ...

Page 6

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC ...

Page 7

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was ...

Page 8

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLT- AGE AND OPERATING FREE-AIR TEMPERATURE (Commercial 5.0V ...

Page 9

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 30pF (Commercial: V ...

Page 10

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 SIGNAL DESCRIPTION MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by ...

Page 11

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Refer ...

Page 12

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 FIFO WRITE/READ OPERATION The state of the Port A data (A0-A35) outputs is controlled by Port A ...

Page 13

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. ...

Page 14

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC) These are dual purpose flags. In FWFT mode, the Input Ready (IRA ...

Page 15

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 data appear on A18-A35. (In this case, A0-A17 are indeterminate.) For a 9- bit bus size, 9 ...

Page 16

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 BYTE ORDER ON PORT A: BYTE ORDER ON PORT B: BE SIZEB SIZEB L ...

Page 17

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 BYTE ORDER ON PORT A: BYTE ORDER ON PORT B: BE SIZEB SIZEB L ...

Page 18

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKA 1 CLKB t RSTS MRS1 BE/FWFT SPM FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA ...

Page 19

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKA 1 CLKB t RSTS PRS1 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 ...

Page 20

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKA 4 MRS1, MRS2 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FFA/IRA ENA ...

Page 21

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLK t t CLKH CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 ...

Page 22

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKC FFC/IRC HIGH t ENS2 MBC t ENS2 WENC t DS C0-C8 DATA SIZE TABLE FOR BYTE ...

Page 23

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKB EFB/ORB HIGH CSB MBB t ENS2 RENB t MDV t EN B0-B8 (Standard Mode) t MDV ...

Page 24

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKA CSA LOW HIGH WRA t t ENS2 MBA t t ENS2 ENH ENA IRA HIGH t ...

Page 25

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKA CSA LOW WRA HIGH t ENS2 t MBA t t ENS2 ENH ENA FFA HIGH t ...

Page 26

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKC t ENS2 MBC t ENS2 WENC IRC HIGH C0-C17 Write ...

Page 27

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKC t ENS2 MBC t ENS2 WENC FFC HIGH Write 1 ...

Page 28

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLK t t CLKH CLKL CLKB CSB LOW LOW MBB t ENS RENB ORB HIGH t ...

Page 29

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLK t t CLKH CLKL CLKB CSB LOW LOW MBB t ENS2 RENB EFB HIGH t ...

Page 30

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA ...

Page 31

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA ...

Page 32

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKC t t ENH ENS2 t ENS2 WENC t SKEW2 CLKA AEA X2 Words in FIFO2 ENA ...

Page 33

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 CLKA t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA A0-A35 CLKB MBF1 CSB ...

Page 34

IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 512 and 1,024 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5V Input Data, 1.5V Enable Input VOLTAGE ...

Page 35

ORDERING INFORMATION XXXXXX X XX Device Type Power Speed Package NOTES: 1. Industrial temperature range is available by special order. 2. Green parts available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 10/06/2000 pgs ...

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