IDT72V2113L7-5PF IDT, Integrated Device Technology Inc, IDT72V2113L7-5PF Datasheet - Page 17

• Manufacturer Part Number: IDT72V2113L7-5PF
• Description: IC FIFO SUPERSYNCII 7-5NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2113L7-5PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 5ns
• Word Size: 18/9Bit
• Organization: 256Kx18/512Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 133.3MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V2113L7-5PF

SERIAL PROGRAMMING MODE
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written,
one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 36 bits for the
IDT72V2103 and 38 bits for the IDT72V2113. For any other mode of operation
(that includes x18 bus width on either the Input or Output), minus 2 bits from the
values above. So, a total of 34 bits for the IDT72V2103 and 36 bits for the
IDT72V2113. See Figure 15, Serial Loading of Programmable Flag Regis-
ters, for the timing diagram for this mode.
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
D
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus t
after the next two rising RCLK edges plus t
PARALLEL PROGRAMMING MODE
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and D
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 6 for the IDT72V2103/
72V2113. Refer to Figure 3, Programmable Flag Offset Programming
Sequence, for a detailed diagram of the data input lines D
parallel programming. If the FIFO is configured for an input to output bus width
of x9 to x18, x18 to x9 or x18 to x18, then the following number of write operations
are required. For an input bus width of x18 total of 4 write operations will be
required for the IDT72V2103/72V2113. For an input bus width of x9 a total of
6 will be required for the IDT72V2103/72V2113. Refer to Figure 3, Program-
mable Flag Offset Programming Sequence, for a detailed diagram.
configured for x18 bus width proceeds as follows: when LD and WEN are set
LOW, data on the inputs Dn are written into the LSB of the Empty Offset Register
on the first LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH
transition of WCLK, data are written into the MSB of the Empty Offset Register.
On the third LOW-to-HIGH transition of WCLK, data are written into the LSB of
the Full Offset Register. On the fourth LOW-to-HIGH transition of WCLK, data
are written into the MSB of the Full Offset Register. The fifth LOW-to-HIGH
transition of WCLK, data are written, once again to the Empty Offset Register.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
n
by toggling WEN. When WEN is brought HIGH with LD and SEN restored
If Serial Programming mode has been selected, as described above, then
Using the serial method, individual registers cannot be programmed
Write operations to the FIFO are allowed before and during the serial
From the time serial programming has begun, neither programmable flag
It is not possible to read the flag offset values in a serial mode.
If Parallel Programming mode has been selected, as described above, then
For example, programming PAE and PAF on the IDT72V2103/72V2113
n
input pins. If the FIFO is configured for an input
PAE
plus t
SKEW2
PAF
0
, PAE will be valid
.
-Dn used during
TM
NARROW BUS FIFO
TM
17
NARROW BUS FIFO
Note that for x9 bus width, one extra Write cycle is required for both the Empty
Offset Register and Full Offset Register. See Figure 16, Parallel Loading of
Programmable Flag Registers, for the timing diagram for this mode.
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers. Refer to Figure 3, Programmable
Flag Offset Programming Sequence, for a detailed diagram of the data input
lines D
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing LD HIGH, write operations can be redirected to
the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offset
register in sequence is written to. As an alternative to holding WEN LOW and
toggling LD, parallel programming can also be interrupted by setting LD LOW
and toggling WEN.
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus t
RCLK edges plus t
register pointer. The contents of the offset registers can be read on the Q
pins when LD is set LOW and REN is set LOW. If the FIFO is configured for an
input bus width and output bus width both set to x9, then the total number of read
operations required to read the offset registers is 6 for the IDT72V2103/
72V2113. Refer to Figure 3, Programmable Flag Offset Programming
Sequence, for a detailed diagram of the data input lines D
parallel programming. If the FIFO is configured for an input to output bus width
of x9 to x18, x18 to x9 or x18 to x18, then the following number of read
operations are required: for an output bus width of x18 a total of 4 read
operations will be required for the IDT72V2103/72V2113. For an output bus
width of x9 a total of 6 will be required for the IDT72V2103/72V2113. Refer to
Figure 3, Programmable Flag Offset Programming Sequence, for a detailed
diagram. For example, reading PAE and PAF on the IDT72V2103/72V2113
configured for x18 bus width proceeds as follows: data are read via Q
the Empty Offset Register on the first and second LOW-to-HIGH transition of
RCLK. Upon the third and fourth LOW-to-HIGH transition of RCLK, data are
read from the Full Offset Register. The fifth and sixth transition of RCLK reads,
once again, from the Empty Offset Register. Note that for a x9 bus width, one
extra Read cycle is required for both the Empty Offset Register and Full Offset
Register. See Figure 17, Parallel Read of Programmable Flag Registers, for
the timing diagram for this mode.
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
which timing mode (IDT Standard or FWFT modes) has been selected.
The act of writing offsets in parallel employs a dedicated write offset register
Write operations to the FIFO are allowed before and during the parallel
Note that the status of a programmable flag (PAE or PAF) output is invalid
The act of reading the offset registers employs a dedicated read offset
It is permissible to interrupt the offset register read sequence with reads or
Parallel reading of the offset registers is always permitted regardless of
0
-Dn used during parallel programming.
PAE
plus t
SKEW2
PAF
.
, PAE will be valid after the next two rising
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
0
-Dn used during
JUNE 1, 2010
n
from
0
-Q
n