IDT72V2113L7-5PF IDT, Integrated Device Technology Inc, IDT72V2113L7-5PF Datasheet - Page 31

• Manufacturer Part Number: IDT72V2113L7-5PF
• Description: IC FIFO SUPERSYNCII 7-5NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2113L7-5PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 5ns
• Word Size: 18/9Bit
• Organization: 256Kx18/512Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 133.3MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V2113L7-5PF

NOTES:
1. If the part is empty at the point of Retransmit, the Empty Flag (EF) will be updated based on RCLK (Retransmit clock cycle). Valid data will also appear on the output.
2. OE = LOW: enables data to be read on outputs Q
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
Q
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
WCLK
0
RCLK
WEN
EF
REN
1
PAE
- Q
PAF
= first word written to the FIFO after Master Reset, W
HF
RT
If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
(1)
n
t
ENS
W
x
t
A
t
ENS
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
W
t
RTS
0
-Q
x+1
n
.
2
= second word written to the FIFO after Master Reset.
1
t
A
t
t
TM
ENH
HF
t
SKEW2
1
NARROW BUS FIFO
W
1
TM
(3)
31
NARROW BUS FIFO
2
t
PAFS
2
t
A
W
2
(3)
3
t
PAES
t
A
COMMERCIAL AND INDUSTRIAL
W
TEMPERATURE RANGES
3
(3)
JUNE 1, 2010
t
t
A
ENH
6119 drw16
W
4