IDT72V2113L7-5PF IDT, Integrated Device Technology Inc, IDT72V2113L7-5PF Datasheet - Page 5

• Manufacturer Part Number: IDT72V2113L7-5PF
• Description: IC FIFO SUPERSYNCII 7-5NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2113L7-5PF

• Function: Synchronous
• Memory Size: 4.7Mb (262k x 18)
• Access Time: 5ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 5ns
• Word Size: 18/9Bit
• Organization: 256Kx18/512Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 133.3MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V2113L7-5PF

to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during master reset by the state of the Programmable Flag
Mode (PFM) pin.
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
to Figure 13 and 14 for Retransmit Timing with zero-latency.
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
The Retransmit function allows data to be reread from the FIFO more than
If zero-latency retransmit operation is selected the first data word to be
Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer
A Big-Endian/Little-Endian data word format is provided. This function is
IW
H
H
L
L
OW
H
H
L
L
TM
NARROW BUS FIFO
TM
5
NARROW BUS FIFO
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin.
to select the parity bit in the word loaded into the parallel port (D
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D
programming of the flag offsets. If Non-Interspersed Parity mode is selected, then
D
during Master Reset by the state of the IP input pin. This mode is relevant only
when the input width is set to x18 mode. Interspersed Parity control only has
an effect during parallel programming of the offset registers. It does not effect the
data written to and read from the FIFO.
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
cron CMOS technology.
8
is assumed to be a valid bit and D
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
A JTAG test port is provided, here the FIFO has fully functional Boundary
If, at any time, the FIFO is not actively performing an operation, the chip will
The IDT72V2103/72V2113 are fabricated using IDT’s high speed submi-
Write Port Width
x18
x18
x9
x9
16
and D
COMMERCIAL AND INDUSTRIAL
17
are ignored. IP mode is selected
Read Port Width
TEMPERATURE RANGES
x18
x18
x9
x9
8
during the parallel
JUNE 1, 2010
0
-D
n
) when