CA3096C Intersil, CA3096C Datasheet - Page 12

• Manufacturer Part Number: CA3096C
• Description: NPN/PNP Transistor Arrays
• Manufacturer: Intersil

Typical Performance Curves
Metallization Mask Layout
Dimensions in parentheses are in millimeters and are derived from the
basic inch dimensions as indicated. Grid graduations are in mils (10
inch).
The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees instead of 90 degrees with respect to the face of the chip.
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
6
5
4
3
2
1
0
FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)
0
40
30
20
10
CA3096, CA3096A, CA3096C
0
(Continued)
1
0
2
10
3
4-10 (0.102-0.254)
C
(0.940-1.143)
BIAS VOLTAGE (V)
BC
CA3096H
37-45
4
C
20
12
BE
5
30
6
C
BI
7
40
(0.940-1.143)
8
37-45
9
10
-3