AD9520-0 Analog Devices, Inc., AD9520-0 Datasheet - Page 77

• Manufacturer Part Number: AD9520-0
• Description: 12 Lvpecl/24 Cmos Output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
192
192
192
193
193
194
194
194
194
194
195
195
195
196
196
197
[2]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
[2]
[1]
[0]
[7:4]
[3:0]
[7]
Channel 0 power-down
Channel 0 direct-to-output
Disable Divider 0 DCC
Divider 1 low cycles
Divider 1 high cycles
Divider 1 bypass
Divider 1 ignore SYNC
Divider 1 force high
Divider 1 start high
Divider 1 phase offset
Channel 1 power-down
Channel 1 direct-to-output
Disable Divider 1 DCC
Divider 2 low cycles
Divider 2 high cycles
Divider 2 bypass
Description
Channel 0 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into safe power-
down mode by setting this bit.)
Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to VCO or CLK.
[1] = 0; OUT0, OUT1, and OUT2 are connected to Divider 0 (default).
[1] = 1;
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0, OUT1, and OUT2.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0, OUT1, and OUT2.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Channel 1 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into safe power-
down mode by setting this bit.)
Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to VCO or CLK.
[1] = 0; OUT3, OUT4, and OUT5 are connected to Divider 1 (default).
[1] = 1;
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT3, OUT4, and OUT5.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT3, OUT4, and OUT5.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x1 means the divider is low for two input clock cycles (default: 0x1).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x1 means the divider is high for two input clock cycles (default: 0x1).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
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AD9520-0