D63711 NEC, D63711 Datasheet - Page 46

• Manufacturer Part Number: D63711
• Description: Search -----> UPD63711
• Manufacturer: NEC

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command input, are described below. As shown below, the ECT register consists of an error counter in the upper 4
bits and a frame counter in the lower 4 bits.
[Functional description]
F[3:0]:
E[3:0]:
46
MSB
E3
The contents of the internal register ECT of the LSI, which were read by AH parameter input following F2H
Remark The mark * indicates the contents set after a reset.
Peak level data is described below.
PKLU: L channel peak level data (upper 8 bits)
PKLD: L channel peak level data (lower 8 bits)
PKRU: R channel peak level data (upper 8 bits)
PKRD: R channel peak level data (lower 8 bits)
The maximum value of both the L channel and R channel in the a subcode 1 frame can be read.
Data is output as 16 bits divided into 8 upper bits and 8 lower bits.
The CC flag must be checked when reading peak level data.
Whenever the Q code is updated, the value of this counter is incremented (0
CRC error occurs, the Q code is not updated and the value of the counter does not change.
This counter indicates the CRC error state. If a CRC error occurs, the counter value is incremented (with a
limit of FH). If an error does not occur, the value of the counter is reset (0H).
E2
E1
E0
F3
Preliminary Product Information S14470EJ1V1PM00
F2
F1
LSB
F0
E[3:0]
F[3:0]
1
Frame Counter
* F[3:0] = 0000
* E[3:0] = 1111
Error Counter
...
F
0...). If a
PD63711