D63711 NEC, D63711 Datasheet - Page 8

• Manufacturer Part Number: D63711
• Description: Search -----> UPD63711
• Manufacturer: NEC

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8
Pin No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Pin Name
LRCKIN
D.GND
D.GND
SCKIN
HOLD/
WDCK
WFCK
DOUT
SCKO
MIRR/
FLAG
LRCK
C16M
LOCK
RFCK
PLCK
PACK
LIMIT
D.V
C1D1
C1D2
C2D1
C2D2
C2D3
D.V
DIN
Tx
DD
DD
Flag output pin indicating that the data currently being output was configured with
uncorrectable data. (Active high)
Serial data input pin to on-chip DAC
If a DSP (etc.) is not connected, this must be shorted with the DOUT pin.
Serial sound data output pin
Serial clock input pin to on-chip DAC
Sound data output from DOUT changes with the falling of this clock. Ensure that
the system connected in the next stage captures the data at the rising of this
signal.
LRCK signal input pin to on-chip DAC
Signal that distinguishes left channel and right channel of sound data output from
DOUT
Defect detection output pin (HOLD)
Pin that outputs a signal twice the frequency of LRCK (88.2 kHz) (WDCK)
HOLD and WDCK can be switched by microcontroller.
Data output pin of digital audio interface
Logic circuit GND
Buffering output pin of oscillation clock
The state of this pin is output in Bit5 of the status output.
Positive power supply pin to logic circuit
EFM synchronization detection signal
This is high level if the frame counter output matches the synchronization pattern
detection signal in the EFM demodulation block, and low level if they do not
match.
Frame synchronization signal of XTAL system
This is the divided crystal resonator clock and indicates a period of one frame
(7.35 kHz).
Mirror output pin (MIRR)
Frame synchronization signal of PLL system. This signal is a signal with a
frequency that is a division of the basic frequency (44.1 kHz) of the read signal
acquired from the PLL system and is approximately equal to 1 frame cycle (7.35
kHz) (WFCK).
MIRR and WFCK can be switched by microcontroller.
Pin for bit clock monitor
When a PLL lock occurs, the falling edge of this signal locks to the EFM signal.
Logic circuit GND
Output pins that indicate the results of C1 error correction
These pins are defined until the falling edge of RFCK.
Output pins that indicate the results of C2 error correction
These pins are defined until the falling edge of RFCK.
Positive power supply pin to logic circuit
PACK synchronization signal of CD-TEXT
The fall of this signal indicates the beginning of the pack.
Preliminary Product Information S14470EJ1V1PM00
Description
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
I
I
I
I
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
PD63711
–
L
–
–
L
–
–
–
–
–
–