LTC2274 Linear Technology, LTC2274 Datasheet - Page 12

• Manufacturer Part Number: LTC2274
• Description: 105Msps Serial Output ADC
• Manufacturer: Linear Technology

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LTC2274
V
GND with 0.1μF ceramic chip capacitors.
GND (Pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40):
ADC Power Ground.
A
A
ENC
sampled analog input is held on the rising edge of ENC
This pin is internally biased to 1.6V through a 6.2kΩ resistor.
Output data can be latched on the falling edge of ENC
ENC
sampled analog input is held on the falling edge of ENC-.
This pin is internally biased to 1.6V through a 6.2kΩ
resistor. Bypass to ground with a 0.1uF capacitor for a
single-ended Encode signal.
DITH (Pin 15): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
ISMODE (Pin 16): Idle Synchronization mode. When IS-
MODE is not asserted, synchronization is performed with
a series of COMMAS (K28.5). When ISMODE is asserted,
a special Idle SYNC mode is enabled where synchroniza-
tion is performed by sending a COMMA (K28.5) followed
by the appropriate data code-group (D5.6 or D16.2) for
establishing a negative running disparity for the fi rst data
code-group after synchronization.
SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with
the SRR1 pin to select the sample rate operating range.
SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with
the SRR0 pin to select the sample rate operating range.
SHDN (Pins 19, 20): Shutdown Pins. A high level on both
pins will shut down the chip.
PIN FUNCTIONS
12
DD
IN
IN
+
–
+
–
(Pins 1, 2, 12, 13 ): Analog 3.3V Supply. Bypass to
(Pin 4): Positive Differential Analog Input.
(Pin 5): Negative Differential Analog Input.
(Pin 10): Negative Differential Encode Input. The
(Pin 9): Positive Differential Encode Input. The
+
.
+
.
OV
This supply range is 1.2V to V
outputs, or 1.4V to OV
terminated CML outputs. Bypass to ground with 0.1μF
ceramic chip capacitor.
CMLOUT
CMLOUT
SYNC
Low for Compatibility with JESD204). A low level on this
pin for at least two sample clock cycles will initiate frame
synchronization.
SYNC
level on this pin for at least two sample clock cycles will
initiate frame synchronization. For single-ended operation,
bypass to ground with a 0.1μF capacitor and use SYNC
as the SYNC point.
FAM (Pin 31): Frame Alignment Monitor Enable. A high
level enables the substitution of predetermined data at the
end of the frame with a K28.7 symbol for frame alignment
monitoring.
PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select
a test pattern for the serial interface.
PAT1 (Pin 33): Pattern Select Bit1. Use with PAT0 to select
a test pattern for the serial interface.
SCRAM (Pin 34): Enable Data Scrambling. A high level on
this pin will apply the polynomial 1 + x
bling each ADC data sample. The scrambling takes place
before the 8B/10B encoding.
PGA (Pin 35): Programmable Gain Amplifi er Control
Pin. Low selects a front-end gain of 1, input range of
2.25V
of 1.5V
MSBINV (Pin 36): Invert the MSB. A high level will invert
the MSB to enable the 2’s complement format.
DD
(Pins 22, 25): Positive Supply for the Output Drivers.
+
–
P-P
P-P
(Pin 29): Sync Request Negative Input. A high
(Pin 28): Sync Request Positive Input (Active
–
+
. High selects a front-end gain of 1.5, input range
.
(Pin 23): Negative High-Speed CML Output.
(Pin 24): Positive High-Speed CML Output.
DD
for AC-coupled or differentially
DD
for directly coupled CML
14
+ x
15
in scram-
2274f
+