LTC2274 Linear Technology, LTC2274 Datasheet - Page 17

• Manufacturer Part Number: LTC2274
• Description: 105Msps Serial Output ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
CONVERTER OPERATION
The core of the LTC2274 is a CMOS pipelined multi-step
converter with a front-end PGA. As shown in Figure 1, the
converter has fi ve pipelined ADC stages. A sampled analog
input will result in a digitized value nine clock cycles later
(see the Timing Diagram section). The analog input (A
A
munity and to maximize the input range. Additionally, the
differential input drive will reduce even order harmonics
of the sample and hold circuit. The encode clock input
(ENC
mode noise immunity.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC, and an error residue amplifi er. The
function of each stage is to produce a digital representation
of its input voltage along with the resulting analog error
residue. The ADC of each stage provides the quantization,
and the residue is produced by taking the difference between
the input voltage and the output of the reconstruction DAC.
The residue is amplifi ed by the residue amplifi er and passed
on to the next stage. The successive stages of the pipeline
operate on alternating phases of the clock so that when
odd stages are outputting their residue, the even stages
are acquiring that residue and vice versa.
IN
–
) is differential for improved common mode noise im-
+
, ENC
–
) is also differential for improved common
IN
+
,
The pipelined ADC of the LTC2274 has two phases of
operation determined by the state of the differential
ENC
ENC
ENC
When ENC is low, the analog input is sampled differentially
onto the input sample-and-hold capacitors, inside the “S/H
& PGA” block of Figure 1. On the rising edge of ENC, the
voltage on the sample capacitors is held. While ENC is
high, the held input voltage is buffered by the S/H amplifi er
which drives the fi rst pipelined ADC stage. The fi rst stage
acquires the output of the S/H amplifi er during the high
phase of ENC. On the falling edge of ENC, the fi rst stage
produces its residue which is acquired by the second stage.
The process continues to the end of the pipeline.
Each ADC stage following the fi rst has additional error
correction range to accommodate fl ash and amplifi er offset
errors. Results from all of the ADC stages are digitally
delayed such that the results can be properly combined
in the correction logic before being encoded, serialized,
and sent to the output buffer.
+
+
–
/ENC
greater than ENC
as ENC low.
–
input pins. For brevity, the text will refer to
–
as ENC high and ENC
LTC2274
+
less than
17
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