74F74SCX Fairchild Semiconductor, 74F74SCX Datasheet
74F74SCX
Specifications of 74F74SCX
Available stocks
Related parts for 74F74SCX
74F74SCX Summary of contents
Page 1
... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 1999 Fairchild Semiconductor Corporation the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: ...
Page 2
Unit Loading/Fan Out Pin Names Data Inputs Clock Pulse Inputs (Active Rising Edge Direct Clear Inputs (Active LOW Direct Set Inputs (Active ...
Page 3
Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...
Page 4
AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL Propagation Delay PLH PHL ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14A Package Number M14D 5 www.fairchildsemi.com ...
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...