IC F/F DL D POS EDGE TRIG 14SOIC

74F74SC

Manufacturer Part Number74F74SC
DescriptionIC F/F DL D POS EDGE TRIG 14SOIC
ManufacturerFairchild Semiconductor
Series74F
TypeD-Type
74F74SC datasheet
 


Specifications of 74F74SC

FunctionSet(Preset) and ResetOutput TypeDifferential
Number Of Elements2Number Of Bits Per Element1
Frequency - Clock125MHzDelay Time - Propagation5.3ns
Trigger TypePositive EdgeCurrent - Output High, Low1mA, 20mA
Voltage - Supply4.5 V ~ 5.5 VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
Page 1/6

Download datasheet (60Kb)Embed
Next
74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q, Q) outputs. Information at
the input is transferred to the outputs on the positive edge
of the clock pulse. Clock triggering occurs at a voltage level
of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
Ordering Code:
Order Number
Package Number
74F74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
sets Q to HIGH level
D
LOW input to C
sets Q to LOW level
D
Clear and Set are independent of clock
Simultaneous LOW on C
D
makes both Q and Q HIGH
Package Description
Connection Diagram
DS009469
April 1988
Revised July 1999
and S
D
www.fairchildsemi.com

74F74SC Summary of contents

  • Page 1

    ... Data input is locked out and information present will not be transferred to Ordering Code: Order Number Package Number 74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ...

  • Page 2

    Unit Loading/Fan Out Pin Names Data Inputs Clock Pulse Inputs (Active Rising Edge Direct Clear Inputs (Active LOW Direct Set Inputs (Active ...

  • Page 3

    Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

  • Page 4

    AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL Propagation Delay PLH PHL ...

  • Page 5

    Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14A Package Number M14D 5 www.fairchildsemi.com ...

  • Page 6

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...