st2024c Sitronix Technology Corporation, st2024c Datasheet
st2024c
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st2024c Summary of contents
Page 1
... ST2024C is a low-cost, high-performance, fully static, 8-bit microcontroller designed with CMOS technology. It comes with 8-bit pipeline CPU core, SRAM, timer, LCD driver, I/O port, PSG and mask program ROM. A Ver 2.2 24K 8-bit Single Chip Microcontroller 128-level deep stack Dual clock source : - OSCX: Crystal oscillator: 32 ...
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... ROM LCD RAM Hardware Debounce Port A Pull_up B Timer 1 & controller Event counter PREW PWM DAC DAC clock 32.768K PSG clock oscillator OSCXI OSCXO 2/54 ST2024C SEG4 : : : SEG39 LCD COM0 : : : Driver COM3 SEG0 SEG1 M SEG2 SEG3 Common U COM4 COM5 ...
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... Transition-trigger Interrupt Programmable Timer1 clock source Port-A bit programmable I/O Transition-trigger Interrupt Port-B bit programmable I/O PSG/DAC Output Power supply OSC input pin. For 32768Hz crystal Port-B input OSC output pin. For 32768Hz crystal Port-B input OSC input pin. toward to external resistor 3/54 ST2024C 1/31/08 ...
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... Ver 2.2 4/54 ST2024C 1/31/08 ...
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... ST2024C Unit: µm PAD CENTER NAME X Y 1942.4 SEG34 1759.6 1759.6 SEG33 1823.300 1713.300 1759.6 SEG32 1603.300 1759.6 SEG31 1493.300 1759.6 SEG30 1383.300 1759.6 SEG29 1273.300 1759.6 SEG28 1163 ...
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... The 8-bit Processor Status Register contains seven status flags. Some of the flags are controlled by the program, others may be controlled both by the program and the CPU. The instruction set contains a member of conditional branch instructions which are designed to allow testing of these flags. to perform stack 6/54 ST2024C 1/31/08 ...
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... I : Interrupt disable flag 1 = Interrupt disable 0 = Interrupt enable Bit Zero flag 1 = Zero 0 = Non zero Bit Carry flag 1 = Carry 0 = Non carry * Don’t use “BRK” instruction. Ver 2.2 TABLE 7-1: STATUS REGISTER (P) Bit 5 Bit 4 Bit 3 Bit 7/54 ST2024C Bit 1 Bit 1/31/08 ...
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... A000H FFFFH 8.1 ROM ($A000~$FFFF) The ST2024C has 24K bytes ROM used for program, data and vector address. Vector address mapping : $FFFE Reserved. $FFFC RESET vector. $FFFA Reserved. $FFF8 INTX (PA0) edge interrupter. $FFF6 Reload DAC data interrupter ...
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... IRPT IRT1 - IEBT IEPT IET1 8.2.4 LCD RAM ($0200~$0227) Resident LCD-RAM, accessible through write and read instructions, are organized in 40 bytes for 40x8 LCD display. Note that this area can also be used as data memory. 9/54 ST2024C Bit 2 Bit 1 Bit 0 Default PA[2] PA[1] PA[0] 1111 1111 PB[2] PB[1] PB[0] ...
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... After the system has been operating, a high on this line of a least two clock cycles will cease ST2024C activity. When a positive edge is detected, there is an initialization sequence lasting six clock cycles. Then the interrupt mask flag is set, the decimal mode is ...
Page 11
... INTX edge interrupt disable Ver 2.2 service routine when interrupt occurs. Hardware will automatically clear the Interrupt flag. Bit 6 Bit 5 Bit 4 Bit 3 - IRBT IRPT IRT1 Bit 6 Bit 5 Bit 4 Bit 3 - IEBT IEPT IET1 11/54 ST2024C Bit 2 Bit 1 Bit 0 Default - IRDAC IRX - - 11 1-11 Bit 2 Bit 1 Bit 0 Default - IEDAC IEX - - 00 0-00 1/31/08 ...
Page 12
... ST2024C has four I/O ports, SEGMENT-PORT and COMMON-PORT. In total, ST2024C provides for a maximum of 18 I/O pins with both SEGMENT-PORT and COMMON-PORT being programmed as output ports. For detail pin assignment, please refer to Table 9-6 : PORT NAME PAD NAME PA0/INTX PA1 PA2 PA3 ...
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... IRPT IRT1 - IEBT IEPT IET1 correspondingly, with “1” for output mode, and “0” for input mode. Bit 6 Bit 5 Bit 4 Bit 3 PCA[6] PCA[5] PCA[4] PCA[3] 13/54 ST2024C Bit 2 Bit 1 Bit 0 Default PA[2] PA[1] PA[0] 1111 1111 PCA[2] PCA[1] PCA[0] 0000 0000 - PSG0 PSGB 100 - - -00 ...
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... The PULL control bit of PMCR controls the ON/OFF of all the pull-up MOS simultaneously. Please refer to the Figure 9-1. VCC PULL-UP DATA INPUT RD_INPUT Bit 6 Bit 5 Bit 4 Bit 3 PDBN INTEG - - 14/54 ST2024C PMOS Bit 2 Bit 1 Bit 0 Default - PSG0 PSGB 100 - - -00 1/31/08 ...
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... CK PCA[4] PA[5] DFF D XNOR2 OR2 CK PCA[5] PA[6] DFF D XNOR2 OR2 CK PCA[6] PA[7] DFF D XNOR2 OR2 CK PCA[7] 15/54 ST2024C PCA ;Set input mode. #$FF PA ;PA be PULL-UP. PA ;Keep last state. <IREQ ;Clear IRQ flag. <IENA ;Enable INT. PA ;Keep last state. Q XNOR2 OR2 Q XNOR2 OR2 Q XNOR2 OR2 Q XNOR2 ...
Page 16
... Port-A interrupt debounce ST2024C has hardware debounce option for Port-A interrupt. The debounce will be enabled with “1” and disable with “0” for PDBN. The debounce will active when Port-A transition occurs, PDBN enable and OSCX enable. TABLE 10-10: PORT CONDITION CONTROL REGISTER (PMCR) ...
Page 17
... Both INTX and PT interrupts will happen sequentially. Pelase refer to the operating steps. Example : . . . RMB0 SMB5 RMB0 SMB0 CLI . . . FIGURE 10-3: INTX Logic Diagram PMCR[5] Falling Edge Interrupt PA 0/INTX 17/54 ST2024C <PCA ;Set input mode. <PMCR ;Rising edge. <IREQ ;Clear IRQ flag. <IENA ;Enable INTX interrupt. 1/31/08 ...
Page 18
... MOS and sound output port separately. Bit 6 Bit 5 Bit 4 Bit PB[3 PDBN INTEG - - correspondingly, with “1” for output mode, and “0” for input mode. Bit 6 Bit 5 Bit 4 Bit 18/54 ST2024C Bit 2 Bit 1 Bit 0 Default PB[2]* PB[1] PB[ -11 - PCB[1] PCB[ -00 - PSG0 PSGB 100 - - -00 Bit 2 Bit 1 Bit 0 Default - PCB[1] PCB[ -00 1/31/08 ...
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... I/O is used as an input. The PULL control bit of PMCR also controls the ON/OFF of all pull-up MOS simultaneously. Please refer to the Figure 9-4. VCC PULL-UP DATA INPUT RD_INPUT Bit 6 Bit 5 Bit 4 Bit 3 PDBN INTEG - - 19/54 ST2024C PMOS Bit 2 Bit 1 Bit 0 Default - PSGO PSGOB 100 - - -00 1/31/08 ...
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... Bit 3 BLANK COMO LENH SEGO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SEGMENT-0 OUTPUT BIT SEGMENT-1 OUTPUT BIT SEGMENT-2 OUTPUT BIT SEGMENT-3 OUTPUT BIT 20/54 ST2024C Bit 2 Bit 1 Bit 0 Default CTR[1] CTR[0] DUTY 0000 0000 Bit 2 Bit 1 Bit 0 Default ???? ???? ???? ???? ???? ???? ...
Page 21
... COM7 output = FLOAT 0 = COM7 output =LOW Ver 2.2 decided by Bit 5 of LCTL[5], Please refer to the following table. Bit 6 Bit 5 Bit 4 Bit 3 BLANK COMO LENH SEGO Bit 6 Bit 5 Bit 4 Bit 3 - 21/54 ST2024C Bit 2 Bit 1 Bit 0 Default - - DUTY 0000 0- -0 Bit 2 Bit 1 Bit 0 Default - - - 0000 - - - - 1/31/08 ...
Page 22
... ST2024C is with dual-clock system. Programmer can choose between OSC(RC) and OSCX(32.768k), or both as clock source through program. The system clock(SYSCK) also can be switched between OSC and OSCX. The OSC will be switch with “0” and OSCX will be switch with “1” for ...
Page 23
... The ST2024C has two timers: Base timer/Timer1, and two prescalers (PRES and PREW). There are two clock sources TABLE 12-19: CLOCK SOURCE (TCLK) FOR PRES SENT 1 0 TABLE 12-20: SUMMARY FOR TIMER REGISTERS Address Name R/W Bit 7 $021 BTM ...
Page 24
... PRES and Timer1 will get a 16bit-event counter. Bit 6 Bit 5 Bit 4 Bit 3 PRS[6] PRS[5] PRS[4] PRS[3] SENA SENT - - timer1. It stops counting only if OSCX stops or hardware reset occurs. 24/54 ST2024C Bit 2 Bit 1 Bit 0 Default PRS[2] PRS[1] PRS[0] 0000 0000 - - - 000 - - - - - 1/31/08 ...
Page 25
... IN1 OUT OUT SEL SEL BTM[2] BTM[1] BTM[ 25/54 ST2024C 8 Bit - UP Counter IRBT CLOCK Base Timer source clock STOP TCLK / 256 TCLK / 32 TCLK / 8 TCLK / 2 OSCX / 256 OSCX / 64 OSCX / 16 OSCX / 4 1/31/08 ...
Page 26
... MUX MUX OUT OUT IN0 IN1 SEL SEL T1M[3] MUX4-1 OUT T1M[4] SEL Bit 6 Bit 5 Bit 4 Bit 3 T1C[6] T1C[5] T1C[4] T1C[3] 26/54 ST2024C D Flip-Flop D Q SYSCK CK 8 Bit - UP Counter IRT1 CLOCK Auto Reload Bit 2 Bit 1 Bit 0 Default T1C[2] T1C[1] T1C[0] 0000 0000 1/31/08 ...
Page 27
... 27/54 ST2024C Clock source Auto-Reload STOP - TCLK / 256 No TCLK / 32 No TCLK / 8 No TCLK / 2 No OSCX / 256 No OSCX / 128 No OSCX / 64 No OSCX / 32 No TCLK / 256 Yes TCLK / 32 Yes TCLK / 8 Yes ...
Page 28
... DACE Ver 2.2 structure of PSG is shown in Figure 12-10 and its clock sources are shown in Figure 12-9. The ST2024C has three PSG playing type.one for channel0(C0) & channel1(C1) square type sound playing.One for ch0 square tone sound and ch1 noise sound.The third sound playing type is DAC PCM playing ...
Page 29
... PCK[1] PCK[0] DMD[1] Bit 6 Bit 5 Bit 4 Bit 3 PDBN INTEG - - Bit 6 Bit 5 Bit 4 Bit 3 (PSGCK must >= 320K Hz) (PSGCK must >= 320K Hz) 29/54 ST2024C Bit 2 Bit 1 Bit 0 Default - PSGO PSGB 100 - - -00 0000 0000 PSG0[9] PSG0[ 0000 0000 0000 PSG1[9] PSG1[ 0000 C1EN C0EN DACE=0 - 000 0000 ...
Page 30
... Frequency of Channel 0 Tone = PSGCK/(1000H-PSG0[11~0])/2 FIGURE 13-12: PSG1[11~8] PSG1[7~0] LOAD C1EN PSGCK Frequency of Channel 1 Tone = PSGCK/(1000H-PSG1[11~0])/2 Ver 2.2 12 Bit Auto-reload Up Counter C0[11~8] OUTPUT C0[7~0] Channel 0 Latch Enable CLOCK Channel1 PSG Tone Counter 12 Bit Auto-reload Up Counter C1[11~8] OUTPUT C1[7~0] Channel 1 Latch Enable CLOCK 30/54 ST2024C Tone out Tone out 1/31/08 ...
Page 31
... SYSCK / 16 100 = SYSCK Ver 2.2 PSG is in tone function. Noise or tone function is selected by PRBS. Bit 6 Bit 5 Bit 4 Bit 3 PCK[2] PCK[1] PCK[0] PRBS PCK[2] PCK[1] PCK[0] DMD[1] 31/54 ST2024C Bit 2 Bit 1 Bit 0 Default C1EN C0EN DACE=0 - 000 0000 DMD[0] INH DACE=1 - 000 0000 1/31/08 ...
Page 32
... PB1 or PB0 in order PSG output. Noise or DAC function is defined by DACE. Ver 2.2 16-Stage White Noise Generator NCK OUTPUT CLOCK Writing a “1” to C1EN will enable noise generator when PSG is in noise mode. 32/54 ST2024C OUTPUT Noise out 1/31/08 ...
Page 33
... DAC[6] DAC[5] DAC[4] DAC[3] Bit 6 Bit 5 Bit 4 Bit 3 PCK[2] PCK[1] PCK[0] PRBS PCK[2] PCK[1] PCK[0] DMD[ bit resolution : 8 bit resolution 33/54 ST2024C Bit 2 Bit 1 Bit 0 Default - PSG0 PSGB 100 - - -00 0000 0000 PSG1[9] PSG1[ 0000 DAC[2] DAC[1] DAC[0] 0000 0000 C1EN C0EN DACE=0 ...
Page 34
... FIGURE 14-14: DAC Generator Diagram PWM Generator DAC[7~0] PO DMD[0] DMD[1] Fs Output Fs POB Enable Reload_DAC FIGURE 14-15: Clock Source for DAC PSGCK Output 0 X Select 34/54 ST2024C BD BDB Reload_DAC PSGC PSGCK 0 0 SYSCK SYSCK SYSCK SYSCK/ SYSCK 1/31/08 ...
Page 35
... They are depended on the application used. The DAC mode is controlled by DMD[1~0 100% high. As the value goes from 0 to -64, the duty cycle decreases from 50% high to 0%. PB0 is inverse of PB1’s waveform. Figure 13-15 shows the PB1 wave-forms DAC = 32 DAC = -32 ST2024C 330 ohm P B1 35/54 ST2024C (TABLE 13-31) 64+X 96 64-X DAC = X SPK 8050 1/31/08 ...
Page 36
... For a negative output value x=0 to -127, PB0 goes low for |X| segments while PB1 stays low. Two-Pin Two Ended PWM DAC Wave-form 32 96 DAC = DAC = -48 vdd ST2024C SPK 2.5K PSGOB 8050 PSGO 2.8K 36/54 ST2024C 96 127 32 DAC = 96 DAC = 127 DAC = 0 DAC = -128 4.7uf 1 1/31/08 ...
Page 37
... PB1 goes high for X segments while PB0 stays low. For a negative output value x=0 to -127, PB0 goes high for |X| segments while PB1 stays low. Two-Pin Push Pull PWM DAC Wave-form DAC = 32 DAC = DAC = -48 DAC = 0 ST2024C P B0 Buzzer PB1 37/54 ST2024C 127 32 1 DAC = 127 DAC = -128 1/31/08 ...
Page 38
... The ST2024C can drive up to 320 dots of LCD panel directly. The LCD driver can control by 1/4 duty(160 dots) and 1/8 duty (320 dots). LCD block include display RAM ($200~ $227) for storing the display data, 40-segment output pins (SEG0~SEG39), 8-common output pins (COM0~COM7). ...
Page 39
... LCD signal V3 V2 COM0 COM1 COM2 COM3 Phase1 Phase2 V3 SEGx V2 All Off SEGx All Ver 2.2 Example COM3 COM2 COM1 COM0 V3 V2 SEGx V1 V0 Phase1 V3 V2 SEGx V1 V0 39/54 ST2024C SEGx SEGx+1 Phase2 1/31/08 ...
Page 40
... LCD signal COM0 COM1 COM7 SEGx V2 All Off V1 V0 Phase1 V4 V3 SEGx V2 All Ver 2 SEGx Phase2 V4 V3 SEGx 40/54 ST2024C Example COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Phase1 Phase2 1/31/08 ...
Page 41
... ST2024C Bit 2 Bit 1 Bit 0 Default LCK[2] LCK[1] LCK[ 0100 - - - 000 - - - - - - HEAV - - - - - - -0- CTR[1] CTR[0] DUTY 0000 0000 Bit 2 Bit 1 Bit 0 Default LCK[2] LCK[1] LCK[0] - -00 0100 Unit: uA 1/4 Duty power ...
Page 42
... Under 1/8 duty condition with writing a “1” to COMO, LCD output pin COM7~COM4 will be controlled by the SCAN register. (Please refer to 9.5 Common port) Ver 2.2 HEAVY DRIVING LCD MODE CONTROL Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit 3 BLANK COMO LENH SEGO 42/54 ST2024C Bit 2 Bit 1 Bit 0 Default - HEAV - - - - - - - 0- Bit 2 Bit 1 Bit 0 Default CTR[1] CTR[0] DUTY 0000 0000 1/31/08 ...
Page 43
... Bit 1 Bit 2 Bit 3 Bit 4 Bit 1 Bit 2 Bit 3 Bit 4 Bit 1 Bit 2 Bit 3 Bit 4 Bit 1 Bit 2 Bit 3 Bit 4 Bit 1 Bit 2 Bit 3 Bit 4 43/54 ST2024C COM5 COM6 COM7 Bit 5 Bit 6 Bit 7 Bit 5 Bit 6 Bit 7 Bit 5 Bit 6 Bit 7 Bit 5 Bit 6 Bit 7 Bit 5 Bit 6 Bit 7 Bit 5 Bit 6 ...
Page 44
... The ST2024C has three power down modes: WAI-0, WAI-1 and STP. The instruction WAI will enable mode WAI-0 or WAI-1, which are controlled by WAIT(SYS[2]). The 16.1 WAI-0 Mode: When WAIT is cleared, WAI instruction lets MCU enter WAI-0 mode. In the mean time, oscillator circuit is be active and interrupts, timer/counter, and PSG will all be working ...
Page 45
... PORTA, PORTB (IOH = -10mA PORTA, PORTB (IOL= 4mA PORTA, PORTB (IOH = -62mA PORTA, PORTB (IOL= 33mA SEGx 0 COMx PPM [F(3.0)-F(2.5)]/F(3.0)(crystal oscillator) PPM C1= 15 – 30P. 45/ Condition = 4mA OL = 4mA. OL ST2024C 1/31/08 ...
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... FIGURE 17-25: Relation between Operation Voltage & Frequency 4.50 4.00 3.50 3.00 2.50 2.00 1.50 2.2 2.4 2.6 TABLE 17-39: R-Oscillator V.S. Frequency OSCI Resistance 180 K 425 K 940 K 2000 K Ver 2.2 Voltage & Frequency 2.8 3 3.2 3.4 Voltage OSC Frequency 4 MHz 2 MHz 1 MHz 0.5 MHz 46/54 ST2024C RC=4MHz RC=2MHz 3.6 3.8 1/31/08 ...
Page 47
... 18.1 Application 1: VDD : 3V Clock : 32768Hz crystal and 4.0MHz R-oscillator LCD : 1/8 duty, 1/4 bias Input : PORT A Output : COM4~7 ALARM : PB0, PB1 PB2,PB3…....: Crystal mode Ver 2 47/54 ST2024C 1/31/08 ...
Page 48
... Application 2: VDD : 3V Clock : 32768Hz crystal and 4.0MHz R-oscillator LCD : 1/4 duty, 1/3 bias I/O : PORT A ALARM : PB0, PB1 PB2,PB3…....: Input mode Note: Connect one capacitor of 100PF to OSCI stabilize oscillation frequency. This capacitor must be placed close to OSCI. Ver 2.2 48/54 ST2024C 1/31/08 ...
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... ST2024C EVB PCB108 FIGURE 18-26: Ver 2.2 The PCB 108 of ST2024C EVB 49/54 ST2024C 1/31/08 ...
Page 50
... LCD Panel Size ： ______ X ______ dot; LCD Driving: LEVEL ______ (1~32) LCD Frame Rate : OSCX / 512 Port-B[2~3] Option COM[4~7] Option SEG[0~3] Option ST2024C EVB PCB Program file ： ﹒ hex E.V. Board bios version ： Check sum （ See appendix ）： Appendix ： ...
Page 51
... If LCD clock source is from R-OSC, LCD will have no clock in WAI1 and 26 can’t display. Always disable interrupt function(by an “ SEI ” instruction) when modify the 27 IENAL,IENAH,IREQL and IREQH register 28 After Power on ,enter wait 0 mode 0.5s before normal operation Ver 2 Confirmed Item 、 power consumption 、 noise…etc. ） 51/54 ST2024C / / / / Check Note 1/31/08 ...
Page 52
... Frame rate should be around 64Hz. Special Notice not use 32768HZ as system clock. Engineer ____________________ Application Circuit： ： ： ： Note: Connect one capacitor of 100PF to OSCI stabilize oscillation frequency. This capacitor must be placed close to OSCI Ver 2.2 Check Manager ____________________ . 52/54 ST2024C Note 1/31/08 ...
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... Page24 Modify description figure 11-6 to 12-6. Page49 Add PCB 108 of ST2024C EVB photo Page50 Add checklist for customer to confirm ST2024C EVB PCB number……………….2007/5/21 Version1.9 Page22,23 Change register SYS bit4 TEST to Test bit and must be set “0” ...
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... ST2024C is modified from ST2024 The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply ...