sm55161a-80hkcm Austin Semiconductor, Inc., sm55161a-80hkcm Datasheet
sm55161a-80hkcm
Related parts for sm55161a-80hkcm
sm55161a-80hkcm Summary of contents
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... SC SE\ SQ0-SQ15 TRG WE\ M suffix I suffix 1 VRAM SM55161A Production PIN ASSIGNMENT (Top View) 64-Pin Ceramic Flatpack (HKC) DESCRIPTION Address inputs Column-Address Strobe/Byte Selects DRAM Data I/O, Write Mask Data Special Function Select Special-Function Select No Connect/Ground (NOTE: Not connected internally ...
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... Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 VRAM SM55161A Production -80 MIN MAX UNITS 150 210 mA 195 mA NAME PIN No. NAME V DQ1 E8 SS1 ...
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... Table 2 and Table 4 for additional information. Additional features of the 55161A include MASKED FLASH WRITE which allows for data in color register to be written into all the memory locations of a selected row. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 VRAM SM55161A Production ...
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... Refresh Address Refresh Address Row Address Row Address Row Address 5 VRAM SM55161A Production 1 DQ0-DQ15 MNE CASL\ CODE 3 RAS\ CASU\ CASX\ WE --- CBRS CBR CBRN Tap ...
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... In transfer operations, address bits A0–A8 are latched at the first falling edge of CASx\ as the start position (tap) for the serial-data output (SQ0–SQ15). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 VRAM SM55161A Production SAM ...
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... QSF is enabled by SE\; therefore, if SE\ is high, the QSF output is in the high- impedance state. no connect / ground (NC/GND) NC/GND must be tied to system ground or left floating for proper device operation. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 VRAM SM55161A Production ...
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... VRAM SM55161A Production ADDRESS DQ0-DQ15 CASL\ 3 DSF RAS\ RAS\ CASU\ CASX Stop point Row Column Write L Address ...
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... TRG\ is high, or both CASx\ and RAS\ are high (see Figure 1 and Figure 2). The EDO mode functions during all read cycles including DRAM read, page-mode read, and read- modify-write cycles (see Figure 3). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 VRAM SM55161A Production . The rf(MA) ...
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... Austin Semiconductor, Inc. FIGURE 2: DRAM Read Cycle With CASx\-Controlled Output FIGURE 3: DRAM Page-Read Cycle with Extended Output SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 VRAM SM55161A Production ...
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... For late-write or read-modify-write cycles, WE\ is brought low after either or both CASL\ and CASU\ fall. The data is strobed in with data setup and hold times for DQ0 –DQ15 referenced to WE\ (see Figure 6). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 5: Example of an Early-Write Cycle FIGURE 6: Example of a Late-Write Cycle SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 VRAM SM55161A Production ...
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... I/O pin on the falling edge of RAS\, data is not written to that I/ data high (write mask = 1) is strobed into a particular I/O pin on the falling edge of RAS\, data is written to that I/O (see Figure 7). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 VRAM SM55161A Production ...
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... RAS\ is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and is reset only by a CBR refresh (option-reset) cycle (see Figure 8). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 VRAM SM55161A Production ...
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... Figure 10). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 10: Block-Write With Masks SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 VRAM SM55161A Production ...
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... FIGURE 12: DQ12-DQ15 After A Block-Write Operation With Previous Data Of 0 bit 15 1100 0111 1111 1011 0111 1010 2nd 3rd 4th Quad Quad 17 VRAM SM55161A Production Example of Upper Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... If only one CASx\ is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until power is lost or until another load- color-register cycle is performed (see Figure 13 and Figure 14). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 VRAM SM55161A Production ...
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... TRG\ trailing edge in the full-register-transfer read cycle (see Figure 15). CASx\ RAS\ FALL FALL 1 TRG\ WE\ DSF CASx VRAM SM55161A Production ADDRESS DQ0-DQ15 DSF RAS\ CASX\ RAS\ Row Tap X X Address Point Row Tap X X Address Point Austin Semiconductor, Inc ...
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... The tap point loaded during the current transfer cycle determines the state of QSF. QSF also changes state when a boundary between two register halves is reached. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 17: Example Of A Split-Register-Transfer Read After A Full- Register-Transfer Read FIGURE 18: Example Of Successive Split-Register-Transfer-Read Operations SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 VRAM SM55161A Production ...
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... SAM. While in stop-point mode, the SAM is divided into partitions whose length is programmed via row addresses A4– CBR set (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 22). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 22 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 23 VRAM SM55161A Production STOP-POINT LOCATIONS 31, 63, 95, 127, 159, 191, 223, 255, 287, 319, 351, 383, 415, 447, 479, 511 63, 127, 191, 255, 319, 383, 447, 511 127, 255, 383, 511 ...
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... V SYMBOL MIN NOM VRAM SM55161A Production . SS MAX UNIT 5 +0 0.8 V 125 °C Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... MIN 5 Standby tc(P) = MIN 5 Active tc(SC) = MIN See note 4 Standby 5 Active tc(SC) = MIN See note 4 Standby tc(SC) = MIN Active ; MIN. IL c(rd) c(W) c(TRD VRAM SM55161A Production -70 -75 -80 MIN MAX MIN MAX MIN 2.4 2.4 2.4 0.4 0.4 ±10 ±10 ±10 ±10 140 130 180 170 130 120 ...
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... dis(RH dis( dis(WL dis(SE) L are specified when the output is no longer driven. 26 VRAM SM55161A Production TYP MAX UNIT ...
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... Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 27 VRAM SM55161A Production -80 MIN MAX UNIT 150 ns 150 ns 200 150 10,000 ...
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... VRAM SM55161A Production -70 -75 -80 MAX MIN MAX MIN MAX UNIT ...
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... MIN must be observed. Depending on the transition times, this can require additional CASx\ su(WCH) must be observed. Depending on the transition times, this can require additional RAS\ su(WRH) is set to t MIN as a reference. d(RLCL) d(RLCL) 29 VRAM SM55161A Production -70 -75 -80 UNIT ...
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... SDS SDH SZE SZS SWS SWH SWiS SWiH Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 30 VRAM SM55161A Production -80 UNITS ...
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... Austin Semiconductor, Inc. FIGURE 24: READ-CYCLE TIMING WITH CASx\-CONTROLLED OUTPUT SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 31 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 25: READ-CYCLE TIMING WITH RAS\-CONTROLLED OUTPUT SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 32 VRAM SM55161A Production ...
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... Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit SMJ55161A Rev. 1.6 03/05 STATE Don't Care Valid Data L Write Mask Valid Data L Don't Care Valid Data Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 33 VRAM SM55161A Production ...
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... Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit SMJ55161A Rev. 1.6 03/05 STATE Don't Care Valid Data L Write Mask Valid Data L Don't Care Valid Data Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 34 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 28: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD) NOTES: 1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 35 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 29: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (LATE-WRITE LOAD) NOTES: 1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 36 VRAM SM55161A Production ...
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... Write operation with nonpersistent write-per-bit Write operation with persistent write-per-bit SMJ55161A Rev. 1.6 03/05 STATE Don't Care Valid Data L Write Mask Valid Data L Don't Care Valid Data Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 37 VRAM SM55161A Production ...
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... DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write mode (normal, block write, etc.). SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 38 VRAM SM55161A Production ...
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... SMJ55161A Rev. 1.6 03/ Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 39 VRAM SM55161A Production from the falling h(TRG) STATE Don't Care Valid Data L Write Mask Valid Data L Don't Care Valid Data H ...
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... SMJ55161A Rev. 1.6 03/05 STATE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 40 VRAM SM55161A Production Don't Care Valid Data L Write Mask Valid Data L Don't Care Valid Data H Don't Care Write Mask ...
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... DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write mode (normal, block write, etc.). SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 41 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 35: LOAD-COLOR-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD) SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 42 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 36: LOAD-COLOR-REGISTER-CYCLE TIMING (LATE-WRITE LOAD) SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 43 VRAM SM55161A Production ...
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... Austin Semiconductor, Inc. FIGURE 37: BLOCK-WRITE-CYCLE TIMING (EARLY WRITE) SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 44 VRAM SM55161A Production ...
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... Column 7 ( SMJ55161A Rev. 1.6 03/ COLUMN MASK DATA High: No Mask High: No Mask 45 VRAM SM55161A Production STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data Low: Mask Low: Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... Austin Semiconductor, Inc. FIGURE 38: BLOCK-WRITE-CYCLE TIMING (LATE WRITE) SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 46 VRAM SM55161A Production ...
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... Column 7 ( SMJ55161A Rev. 1.6 03/ COLUMN MASK DATA High: No Mask High: No Mask 47 VRAM SM55161A Production STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data Low: Mask Low: Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... Austin Semiconductor, Inc. FIGURE 39: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE TIMING SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 48 VRAM SM55161A Production ...
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... Column 7 ( SMJ55161A Rev. 1.6 03/ COLUMN MASK DATA High: No Mask High: No Mask 49 VRAM SM55161A Production STATE 2 3 Don't Care Valid Data Write Mask Valid Data Don't Care Valid Data Low: Mask Low: Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... Austin Semiconductor, Inc. FIGURE 40: RAS\-ONLY REFRESH-CYCLE TIMING SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 50 VRAM SM55161A Production ...
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... CBR refresh with option reset CBR refresh with no reset CBR refresh with stop-point set and no reset SMJ55161A Rev. 1.6 03/05 STATE 1 2 Don't Care L Don't Care H Stop Address H Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 51 VRAM SM55161A Production ...
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... CBR refresh with option reset CBR refresh with no reset CBR refresh with stop-point set and no reset SMJ55161A Rev. 1.6 03/05 STATE 1 2 Don't Care L Don't Care H Stop Address H Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 52 VRAM SM55161A Production ...
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... Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive transition of SC – A8. D. Early-load operation is defined as t h(TRG) E. There must be no rising transitions. SMJ55161A Rev. 1.6 03/05 MIN < t < t MIN. h(TRG) d(RLTH) 53 VRAM SM55161A Production Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive transition of SC. C. A0–A8. D. Late load operation is defined as t d(THRH) SMJ55161A Rev. 1.6 03/05 < 0 ns. 54 VRAM SM55161A Production Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... Austin Semiconductor, Inc. FIGURE 45: SPLIT-REGISTER-TRANSFER-READ TIMING NOTES: A. A0–A7: tap point of the given half; A8: identifies the DRAM row half SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 55 VRAM SM55161A Production ...
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... B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle. FIGURE 47: SERIAL-WRITE-CYCLE TIMING SMJ55161A Rev. 1.6 03/ Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 56 VRAM SM55161A Production ...
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... B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 57 VRAM SM55161A Production ...
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... RAS\ of the split-register-transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). SMJ55161A Rev. 1.6 03/05 is met the minimum delay time between the rising edge of d(MSRL) d(MSRL) d(RHMS) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 58 VRAM SM55161A Production requirement the d(RHMS) ...
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... FIGURE 50: MASKED WRITE TRANSFER NOTES: 1. SE\ = “L” 2. There must be no rising transitions. 3. QSF = “L” - Lower SAM (0-255) is active. QSF = “H” - Upper SAM (256-511) is active. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 59 VRAM SM55161A Production ...
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... QSF = “L” - Lower SAM (0-255) is active. QSF = “H” - Upper SAM (256-511) is active the SAM start address in before SWT. 4. STOP i and STOP j are programmable stop addresses. SMJ55161A Rev. 1.6 03/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 60 VRAM SM55161A Production ...
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... This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. 6. The pins can be gold plated or solder dipped. 7. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively SMJ55161A Rev. 1.6 03/05 Package Designator GB Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 61 VRAM SM55161A Production ...
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... This package can be hermetically sealed with a metal lid. 4. The terminals are gold plated. 5. All leads not shown for clarity purposes. SMJ55161A Rev. 1.6 03/05 Package Designator HKC SMD 5962-94549, Case Outline Y 62 VRAM SM55161A Production Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...
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... Austin Semiconductor, Inc. EXAMPLE: SM55161A-75GBI Prefix* SM SMX SM SMX SM SMX EXAMPLE: SM55161A-80HKCM Prefix* SM SMX SM SMX SM SMX SM Prefix: Standard Military Processing using MIL-STD-883C flow & methods but non-complaint to para 1.2.1 SMX Prefix: strictly commercial flow samples I suffix: -40C to +85C M suffix: -55C to 125C SMJ55161A Rev. 1.6 03/05 ...
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... ASI Part # TO BE COMPLETED WHEN SMD LISTING IS RELEASED SMJ55161A Rev. 1.6 03/05 CROSS REFERENCE Package Designator HKC SMD Part # ASI Part # TO BE COMPLETED WHEN SMD LISTING IS RELEASED Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 64 VRAM SM55161A Production SMD Part # ...