sm55161a-80hkcm Austin Semiconductor, Inc., sm55161a-80hkcm Datasheet - Page 9

• Manufacturer Part Number: sm55161a-80hkcm
• Description: 262144 X 16 Bit Vram Multiport Video Ram
• Manufacturer: Austin Semiconductor, Inc.

enhanced page mode
access by keeping the same row address while selecting ran-
dom column addresses. This mode eliminates the time required
for row-address setup, row-address hold, and address multi-
plex. The maximum RAS\ low time and CAS\ page cycle time
used determine the number of columns that can be accessed.
page mode allows the SMJ55161A to operate at a higher data
bandwidth. Data retrieval begins as soon as the column
address is valid rather than when CASx\ transitions low. A
valid column address can be presented immediately after the
row-address hold time has been satisfied, usually well in
advance of the falling edge of CASx\. In this case, data is
obtained after t
MAX (access time from column address) has been satisfied.
REFRESH
CAS-before-RAS (CBR) refresh
CASL\ and CASU\ low earlier than RAS\. The external row
address is ignored, and the refresh row address is generated
internally. Three types of CBR refresh cycles are available. The
CBR refresh (option reset) ends the persistent write-per-bit mode
and the stop-point mode. The CBRN and CBRS refreshes (no
reset) do not end the persistent write-per-bit mode or the stop-
point mode. The 512 rows of the DRAM do not necessarily
FIGURE 1: DRAM Read Cycle With RAS\-Controlled Output
SMJ55161A
Rev. 1.6 03/05
Enhanced page-mode operation allows faster memory
Unlike conventional page-mode operations, the enhanced
CBR refreshes are accomplished by bringing either or both
a(C)
MAX (access time from CASx\ low) if t
Austin Semiconductor, Inc.
a(CA)
9
need to be refreshed consecutively as long as the entire refresh
is completed within the required time period, t
output buffers remain in the high-impedance state during the
CBR refresh cycles regardless of the state of TRG\.
hidden refresh
and CASU\ low in the DRAM read cycle and cycling RAS\. The
output data of the DRAM read cycle remains valid while the
refresh is carried out. Like the CBR refresh, the refreshed row
addresses are generated internally during the hidden refresh.
RAS-only refresh
every row address. Unless CASx\ and TRG\ are low, the output
buffers remain in the high-impedance state to conserve power.
Externally-generated addresses must be supplied during RAS\-
only refresh. Strobing each of the 512 row addresses with RAS\
causes all bits in each row to be refreshed.
extended data output
The SMJ55161A features EDO during DRAM accesses. While
RAS\ and TRG\ are low, the DRAM output remains valid. The
output remains valid even when CASx\ returns high until WE\
is low, TRG\ is high, or both CASx\ and RAS\ are high (see
Figure 1 and Figure 2). The EDO mode functions during all read
cycles including DRAM read, page-mode read, and read-
modify-write cycles (see Figure 3).
A hidden refresh is accomplished by holding both CASL\
A RAS\-only refresh is accomplished by cycling RAS\ at
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Production
SM55161A
VRAM
rf(MA)
. The