sm55161a-80hkcm Austin Semiconductor, Inc., sm55161a-80hkcm Datasheet - Page 58

• Manufacturer Part Number: sm55161a-80hkcm
• Description: 262144 X 16 Bit Vram Multiport Video Ram
• Manufacturer: Austin Semiconductor, Inc.

FIGURE 49: SPLIT-REGISTER OPERATING SEQUENCE
NOTES:
A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer cycle. This is
necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-register-transfer-read cycle
(CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no
minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle.
B. A split-register transfer into the inactive half is not allowed until t
the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register-transfer cycle into the inactive half. After the
t
minimum delay time between the rising edge of RAS\ of the split-register-transfer cycle into the inactive half and the rising edge of the serial
clock of the last bit (bit 255 or 511).
SMJ55161A
Rev. 1.6 03/05
d(MSRL)
requirement is met, the split-register transfer into the inactive half must also satisfy the minimum t
Austin Semiconductor, Inc.
d(MSRL)
58
is met. t
d(MSRL)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
is the minimum delay time between the rising edge of
d(RHMS)
requirement. t
Production
SM55161A
VRAM
d(RHMS)
is the