isl5757 Intersil Corporation, isl5757 Datasheet - Page 10

• Manufacturer Part Number: isl5757
• Description: 10-bit, +3.3v, 260+msps, High Speed D/aconverter
• Manufacturer: Intersil Corporation

(nominally +3.3V) to maintain optimum SFDR. However,
operation down to +2.7V is possible with some degradation
in SFDR. Reducing the analog output current can help the
SFDR at +2.7V. The SFDR values stated in the table of
specifications were obtained with a +3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DV
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a ±40ppm/°C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(16) selects the reference. The internal reference can be
selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (the
analog supply voltage) and the external reference driven into
REFIO, pin 17. The full scale output current of the converter
is a function of the voltage reference used and the value of
R
though operation below 2mA is possible, with performance
degradation.
If the internal reference is used, V
approximately 1.2V (pin 18). If an external reference is used,
V
I
I
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91kΩ R
resistor, then the input coding to output current will resemble
the following:
OUT
OUT
SET
FSADJ
INPUT CODE (D9-D0)
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH
DD
(Full Scale) = (V
. I
(Full Scale) is:
10000 00000
00000 00000
11111 11111
and to the analog ground for AV
OUT
DD
will equal the external reference. The calculation for
and DV
should be within the 2mA to 20mA range,
INTERNAL REFERENCE AND RSET = 1.91kΩ
DD
FSADJ
. Also, the layout should be designed
IOUTA (mA)
/R
10
SET)
20
10
0
FSADJ
X 32.
DD
. Additional filtering
will equal
IOUTB (mA)
SET
10
20
0
ISL5757
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -1.0V to 1.25V. R
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
V
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-single-
ended arrangement to achieve better harmonic rejection.
With R
will provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the DAC is set
to 20mA (used for the electrical specifications table). Values
of R
performance curves. The center tap in Figure 13 must be
grounded.
In the circuit in Figure 14, the user is left with the option to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
IOUT
transformer. If the center tap is grounded, the DC voltage is
0V. Recommended values for the circuit in Figure 14 are
R
performance of Figure 13 and Figure 14 is basically the
same, however leaving the center tap of Figure 14 floating
allows the circuit to find a more balanced virtual ground,
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
OUT
A
= R
DIFF
DC
= I
DIFF
B
x (R
= 50Ω, R
OUT
= 100Ω and R
= 50Ω and R
A
X R
//R
B
DIFF
OUT
) V because R
.
= 100Ω, assuming R
LOAD
LOAD
= 50Ω were used for the typical
= 50Ω, the circuit in Figure 13
DIFF
OUT
is DC shorted by the
LOAD
(the impedance
November 12, 2004
= 50Ω. The
FN6078.1