isl24201 Intersil Corporation, isl24201 Datasheet
isl24201
Related parts for isl24201
isl24201 Summary of contents
Page 1
... C bus interface that is used to read and write to its registers and EEPROM. At power-up the EEPROM value is transferred to the data register and output. The ISL24201 is available 3mm x 3mm TDFN package. This package has a maximum height of 0.8mm for very low profile designs. The ambient operating temperature range is -40° ...
Page 2
... PAD WP 3 GND 4 (THERMAL PAD CONNECTS TO GND) 2 ISL24201 VDD DAC REGISTERS 8-BIT EEPROM CURRENT SINK ISL24201 GND FIGURE 2. BLOCK DIAGRAM OF THE ISL24201 Pin Descriptions PIN NAME OUT SET 8 SCL 7 SDA 6 A VDD GND V DD SDA SCL SET ...
Page 3
... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page ISL24201. For more information on MSL please see techbrief TB363. 3 ...
Page 4
... WP Input Logic Low Input Hysteresis WPH IL WP Input Leakage Current WPN 4 ISL24201 Thermal Information Thermal Resistance (Typical TDFN Package (Notes 4, 5 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C +0.3V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C DD Pb-free Reflow Profile ...
Page 5
... ISL24201. The output is connected to an external voltage divider, as shown in Figure 3, so that the ISL24201 will have the ability to reduce the voltage on the output by increasing the OUT pin sink current. The amount of current sunk is controlled by the I ...
Page 6
... 256 SET OUT(MAX for transistor Q1. The line labeled DS DS value from Equation 3 OUT(MAX) MINIMUM SATURATION VOLTAGE SATURATION REGION VDS ( FOR THE ISL24201 OUTPUT TRANSISTOR DS DS (EQ. 3) (EQ. 4) being used FN7586.1 December 9, 2010 ...
Page 7
... ------------------- - The span of the V voltage is shown by Equation 8. COM ( ) V SPAN COM SET TH 7 ISL24201 /20 and is added to VDD and SET pins to OUT 0.6 (EQ. 5) 0.5 0.4 R ⎛ ⎞ ⎞ (EQ. 6) ⎜ ⎟ ⎟ ------------------- - 0.3 20R ⎝ ⎠ ⎠ SET 0.2 and R ...
Page 8
... EEPROM programming cycle is completed may result in corrupted data in the EEPROM. Operating and Programming = 4.99kΩ. SET Supply Voltage and Current To program the EEPROM not required, the ISL24201 will operate over an A 4.5V to 19V. During EEPROM programming, I higher than their quiescent currents. Figure 11 shows a typical I and I DD current pulses are Erase and Write cycles ...
Page 9
... Figures 13 and 14 Bus Signals N o The ISL24201 uses fixed voltages for its I than the percentage of V (see Table 3). This should not cause a problem in most systems, 2 but the I C logic levels in a specific design should be checked to ensure they are compatible with the ISL24201 ...
Page 10
... I C Read and Write Format rite tart ISL24201 I C Read Byte 1 6 bit Address Start MSB ISL24201 ...
Page 11
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 11 ISL24201 www.intersil.com/askourstaff For additional products, see www.intersil.com/product_tree www ...
Page 12
... LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW 2X 1.950 PIN #1 1 INDEX AREA 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 12 ISL24201 A B (1.50) ( 2.90 ) PIN 1 (6x 0.65) TYPICAL RECOMMENDED LAND PATTERN 0.75 ±0.05 6X 0.65 1.50 ±0. 0.30 ±0.05 0. NOTES: 1. Dimensions are in millimeters. ...