isl97673 Intersil Corporation, isl97673 Datasheet
isl97673
Related parts for isl97673
isl97673 Summary of contents
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... The ISL97673 has a full range of dimming capabilities 2 that include SMBus/I C controlled PWM dimming or DC dimming. Another key feature of the ISL97673 is that it allows very linear PWM dimming from 0.4% to 100 30kHz. Current matching of 0.4% to 100% dimming achieves ±1% tolerance from 100Hz to 5kHz dimming and ± ...
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... DAC0 - DAC0 PWM0 PWM0 Controls DAC1 DAC1 PWM1 PWM1 Controls DAC5 D AC5 PWM5 Controls ISL97673 FIGURE 2. ISL97673 BLOCK DIAGRAM 40mA 45V*, 25mA per string 78 (6x13) LEDs 4.7uF/50V LX OVP OVP PGND p e Open Ckt, Short Ckt Detects CH0 CH1 CH5 Temp 0 Sensor ...
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... Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97673. For more information on MSL please see techbrief TB363. Pin Descriptions (I = Input Output Supply) ...
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... Switching Frequency........................................14 5V Low Dropout Regulator................................ 14 In-rush Control and Soft-start........................... 14 Fault Protection and Monitoring ......................... 14 Short Circuit Protection (SCP) ........................... 14 Open Circuit Protection (OCP) ........................... 15 4 ISL97673 Overvoltage Protection (OVP) ........................... 15 Undervoltage Lockout ..................................... 15 Input Overcurrent Protection............................ 15 Over-Temperature Protection (OTP) .................. 15 Write Byte ......................................................... 18 Read Byte ......................................................... 18 Slave Device Address.......................................... 18 SMBus/I2C Register Definitions ...
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... Guaranteed Range for EN Input Low Voltage Low EN Guaranteed Range for EN Input High Voltage Hi t EN/PWMI Low Time Before Shut-down ENLow 5 ISL97673 Thermal Information (T = +25°C) A Thermal Resistance (Typical QFN Package (Notes Thermal Characterization (Typical QFN Package (Note ...
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... PWM GENERATOR VIL Guaranteed Range for PWMI Input Low Voltage VIH Guaranteed Range for PWMI Input High Voltage FPWM PWMI Input Frequency Range PWMACC PWM Input Accuracy 6 ISL97673 = +25° 12V, EN/PWM = 5V CONDITION (Note +25°C A 100% LED Duty Cycle ...
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... Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. Independent from the numbers of LEDs, at minimum V minimum V is limited 28V. OUT 10. Limits established by characterization and are not production tested. 7 ISL97673 = +25° 12V, EN/PWM = 5V CONDITION RFPWM = 660kΩ Direct PWM Mode ...
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... CYCLE) 100 90 80 +25° 0°C +85° FIGURE 7. EFFICIENCY TEMPERATURE AT IN 20mA (100% LED DUTY CYCLE) 8 ISL97673 100 FIGURE 4. EFFICIENCY 30mA LED CURRENT IN 100 1.2MHz FIGURE 6. EFFICIENCY vs V 0.40 0.30 0.20 -40°C 0.10 0.00 -0.10 -0.20 -0.30 -0. FIGURE 8 ...
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... DC FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE vs V FIGURE 11. V RIPPLE VOLTAGE, V OUT AT 20mA/CHANNEL FIGURE 13. IN-RUSH AND LED CURRENT AT V FOR 6P12S AT 20mA/CHANNEL 9 ISL97673 (Continued) 0.60 0.55 4 0.50 IN 0.45 0. FIGURE 10 12V, 6P12S FIGURE 12. IN-RUSH and LED CURRENT AT V ...
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... FIGURE 15. LINE REGULATION WITH V FROM 26V TO 6V FOR 6P12S AT 20mA/CHANNEL FIGURE 17. LOAD REGULATION WITH I FROM 100 PWM DIMMING 12V, 6P12S AT 20mA/CHANNEL IN 10 ISL97673 (Continued) CHANGE FIGURE 16. LOAD REGULATION WITH I IN FROM 0% TO 100% PWM DIMMING, V FIGURE 18. ISL97671 SHUTS DOWN AND STOPS CHANGE ...
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... AC/DC adapter without rendering a noticeable visual nuisance. The number of LEDs that can be driven by ISL97673 depend on the type of LED chosen in the application. The ISL97673 are capable of boosting up to 45V and typically driving 13 LEDs in series for each of the 6 channels, enabling a total of 104 pieces of the 3 ...
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... When SEL1 is low and SEL2 is low direct PWM mode such that the dimming follows directly from the applied PWMI signal. Dimming Controls The ISL97673 allow two ways of controlling the LED current, and therefore, the brightness. They are current adjustment 2. PWM chopping of the LED current defined in Step 1. ...
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... The PWM dimming frequency can be set or applied up to 30kHz with duty cycle from 0.4% to 100%. PHASE SHIFT CONTROL The ISL97673 is capable of delaying the phase of each current source to minimize load transients. By default, phase shifting is disabled as shown in Figure 20 where the channels PWM currents are switching uniformly. The ...
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... PD ILED5 FIGURE 23. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY The ISL97673 allows the user to program the amount of phase shift degree in 7-bit resolution, as shown in Figure 24. To enable programmable phase shifting, the user must write to the Phase Shift Control register with EqualPhase = 0 and the desirable phase shift value of PhaseShift[6:0] ...
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... This monitoring happens on a cycle by cycle basis in a self protecting way. Additionally, the ISL97673 monitors the voltage at the LX and OVP pins. At startup, a fixed current is injected out of the LX pins and into the output capacitor. The device will not start up unless the voltage at LX exceeds 1 ...
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... CH0 Open Circuit Upper OTP not with infinite triggered and CH0 < resistance 4V 5 CH0 LED Open Upper OTP not Circuit but has triggered and CH0 < paralleled Zener 4V 16 ISL97673 LX O/P SHORT OVP FET LOGIC DRIVER VSC VSC THRM THRM REF SHDN SHDN ...
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... C Description S = start condition P = stop condition A = acknowledge A = not acknowledge R/W = read enable at high; write enable at low 17 ISL97673 TABLE 2. PROTECTIONS TABLE (Continued) FAILED CHANNEL ACTION All channels go off until chip cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce I ...
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... SMBus/I C protocol. Note: In this document, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid confusion. Therefore, if the device is in the write 18 ISL97673 Command Code A FIGURE 26 ...
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... Si Revision Register 0x07 DC Brightness Control Register 0x08 Configuration Register 0x09 Output Channel Select and Fault Readout Register 0x0A Phase Shift Degree 19 ISL97673 TABLE 3A. REGISTER LISTING BIT 5 BIT 4 BIT 3 BIT 2 BRT5 BRT4 BRT3 Reserved Reserved Reserved PWM_MD 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN 1 ...
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... SMBus Backlight On but stays with previous mode selection FIGURE 30. DESCRIPTIONS OF DEVICE CONTROL REGISTER 20 ISL97673 Operating Modes selected by Device Control Register Bits 1 and 2). • An SMBus/I returns the programmed PWM brightness level. • An SMBus/I the backlight controller to the maximum brightness. • An SMBus/I the backlight controller to the minimum brightness output ...
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... OV_CURR Bit 1 THRM_SHDN Bit 0 FAULT FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER 21 ISL97673 2 C this register are read-only, with the exception of Bit 0, which can be cleared by writing to it. • A Read Byte cycle to Register 0x02 indicates the current BL on/off status in BL_STAT (1 if the the BL is off). ...
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... C Write Byte cycle to Register 0x07 sets the brightness level in DC only. 2 • An SMBus/I C Read Byte cycle to Register 0x07 returns the current DC brightness level. • Default value for Register 0x07 is 0xFF. 22 ISL97673 MFG1 MFG0 REV2 Bit 4 (R) Bit 3 (R) Bit 2 (R) BIT FIELD DEFINITIONS FIGURE 32 ...
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... CH[5..0] CH5 = Channel 5, CH4 = Channel 4 and so FIGURE 35. DESCRIPTIONS OF OUTPUT CHANNEL REGISTER 23 ISL97673 of interest. When reading data from this register, any disabled channel and any faulted out channel will read as 0. This allows the user to determine which channel is faulty and optionally not enabling it in order to allow the rest of the system to continue to function ...
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... where D is the switching duty cycle defined by the turn-on time over the switching period forward voltage that can be neglected for approximation. 24 ISL97673 PHASE- PHASE- SHIFT4 SHIFT3 Bit 4 (R/W) Bit 3 (R/W) BIT FIELD DEFINITIONS 7-bit Phase shift setting - phase shift between each channel is PhaseShift< ...
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... Applications SW SAT High Current Applications Each channel of the ISL97673 can support up to 30mA. For applications that need higher current, multiple channels can be grouped to achieve the desirable current. For example, the cathode of the last LED can be connected to CH0 to CH2, this configuration can be treated as a single string with 90mA current driving capability ...
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... Multiple Drivers Operation For large LCD panels where more than 6 channels of LEDs are needed, multiple ISL97673s with each driver having its own supporting components can be controlled together with the common SMBus/I ISL97673 does not have extra pins strappable slave address feature, but a separate EN signal can be applied to each driver for asynchronous operation ...
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... Package Outline Drawing L20.3x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 3. PIN 1 INDEX AREA A TOP VIEW (2.65) (3.80) (1.65) (2.80) TYPICAL RECOMMENDED LAND PATTERN 27 ISL97673 A B 20X 4 4.00 0.15 (4X) VIEW "A-A" 20x 0.40±0.10 (16 x 0.50) (20 x 0.25) (20 x 0.60) NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSE Y14.5m-1994. ...