isl97652 Intersil Corporation, isl97652 Datasheet - Page 17

• Manufacturer Part Number: isl97652
• Description: 4-channel Integrated Lcd Supply With Dual Vcom Amplifiers
• Manufacturer: Intersil Corporation

The maximum V
R5 and R6 in the Typical Application Diagram determine
V
Charge Pump Supply
The magnitude of the SUP supply will determine the charge
pump diode configuration; whether x2 or x3 for the positive
charge pump or x1 or x2 for the negative charge pump.
An independent charge pump supply pin 13 (SUP) is
provided and this may be connected to Vin, Vmain, AVDD or
some other suitable supply.
Note that if AVDD is chosen for the SUP supply, then a
potential fault-like interaction with the supply sequencing
and fault checking is present; when EN1 goes high (with
EN2 low), fault checking on the VOFF charge pump is
started by the voltage ramp on DEL1. If this pin reaches
~1.9V before VOFF is within 90% of it's regulation voltage
then the buck converter (Tcon bias) and Voff will be
continually re-started. This condition will arise if the SUP
supply has not been activated by EN2 going high before
DEL1 has reached 1.9V. One solution would be to increase
the capacitance on DEL1 to overlap enough in time with the
EN2 going high. This does have the disadvantage of
lengthening the fault detection time of the VOFF charge
pump under true fault conditions and it also lengthens the
initial VOFF turn-on time. Another solution would be to
supply SUP from Vmain as long as the magnitude of Vmain
V
V
OFF_MAX
OFF
OFF
output voltage.
=
V
FBN
(
2x
)
FAULT
•
=
⎛
⎝
OFF
1
–
+
V
F
R6
------- -
R5
SUP
OSC
output voltage of a single stage charge pump is:
⎞
⎠
A2
CLK
EN
–
+
V
V
REF
DIODE
17
0.53V
STOP
•
CONTROL
⎛
⎝
R6
------- -
R5
PWM
+
2 I
⎞
⎠
A1
FIGURE 19. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
•
VDC
OUT
•
(
0.5V
R
ON
(EQ. 19)
(
NOUT
M2
M1
)H
ISL97652
V
+
DRVN
SUP
GND
FBN
R
ON
(
NOUT
820pF
(without the boost running) is large enough to satisfy the
regulated VOFF supply.
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at
the FBP and FBN inputs, which may degrade load regulation
performance, can be reduced by the inclusion of capacitors
across the feedback resistors (e.g. in the Application
Diagram, C4 and C5 for the positive charge pump).
Set R7 • C4 = R8 • C5 with C4 ~ 100pF.
V
The Von slice circuit functions as a three way multiplexer,
switching VGHM between ground, VGL and VGH (typ 15-
30V). Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). HIGH to LOW delay and slew
control is provided by external components on pins CE and
RE respectively. The block diagram of the VON-SLICE
circuit is shown in Figure 3.
When VDPM is LOW, the block is disabled and VGHM is
grounded.
When VDPM is HIGH, VGHM is determined by VFLK; when
VFLK goes LOW, there is a delay controlled by the capacitor
attached to the CE pin, following which VGHM is driven to
VGL, with a slew rate controlled by the resistor attached to
the RE pin. Note that VGL is used only as a reference
voltage for an amplifier, thus does not have to source or sink
a significant DC current. When VFLK goes HIGH, VGHM is
ON-SLICE
C2
0.1µF
)L
C
)
V
N
REF
R5
40.2k
Circuit Operation
D3
100pF
453k
C3
R6
D4
C
1µF
OFF
V
OFF
(-8V)
November 2, 2007
(EQ. 18)
FN9287.1