isl6146afuz Intersil Corporation, isl6146afuz Datasheet
isl6146afuz
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isl6146afuz Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners Vth for Noise Immunity ...
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Block Diagram Q-PUMP BIAS VDS FORWARD + REGULATOR VIN 20mV VOUT REVERSE DETECTION COMPARATOR 55mV + ENABLE * ADJ HIGH SPEED + COMPARATOR * Connected to BIAS on ISL6146A/B Connected to VOUT on ISL6146C Pin Configuration ISL6146A, ISL6146B GATE 1 ...
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... The second sensing node for external FET control and connected to the Load side (ORing MOSFET Drain). This is the common connection point for multiple paralleled supplies. V off. Range 24V PAD Thermal Connect to GND Pad Ordering Information PART NUMBER (Notes ISL6146AFUZ (Note 4) ISL6146AFRZ ISL6146BFUZ (Note 4) ISL6146BFRZ ISL6146CFUZ (Note 4) ISL6146CFRZ ISL6146AEVAL1Z ISL6146BEVAL1Z ISL6146CEVAL1Z NOTES: 1. Add “ ...
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Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Absolute Maximum Ratings BIAS, VIN, VOUT ...
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Electrical Specifications V temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETERS t Fast Turn-off Time toff t Slow Turn-off Time toffs I Turn-On Current ON V GATE to V Rising Fault Voltage VG_FLTr IN V GATE to V Falling Fault ...
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Electrical Specifications V temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETERS t EN/UVLO Falling to GATE Falling Delay EN2GTEF EN/OVP Rising to GATE Falling Delay Ren_h ENABLE Pull-Down Resistor Ren_l ENABLE Pull-Up Resistor Vadj ADJ Pin Voltage Radj ADJ Pull-Up ...
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Typical Performance Curves 4.0 3.5 3.0 2.5 18V DISABLED 12V DISABLED 3V DISABLED 2.0 1.5 1.0 -40 25 TEMPERATURE (°C) FIGURE 3. ISL6146A/B BIAS AND ISL6146C V TEMPERATURE 35 BIAS = 18V 30 BIAS = 12V BIAS ...
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Typical Performance Curves 750 OVP RISING 700 650 600 UVLO RISING AND OVP FALLING 550 500 450 -40 25 TEMPERATURE (°C) FIGURE 9. ISL6146C UVLO/OVP Vth vs TEMPERATURE 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 -40 ...
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Typical Performance Curves -40 25 TEMPERATURE (°C) FIGURE 15. HIGH SPEED COMPARATOR OFFSET VOLTAGE 900 800 R ADJ 700 600 500 400 300 200 100 R TO GND = 100k ADJ 0 -40 ...
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Typical Performance Curves GATE1 IIN1 FIGURE 21. ISL6146C SLOW RAMP CONNECT 12V ORing GATE1 IIN2 FIGURE 23. ISL6146C HOT SWAP CONNECT 12V ORing EN/UVLO FIGURE 25. ISL6146A EN/ISL6146C UVLO TO GATE ON DELAY 11 ISL6146 (Continued) GATE 2 GATE 2 ...
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Typical Performance Curves EN FIGURE 27. ISL6146B EN TO GATE ON DELAY OVP FIGURE 29. ISL6146C OVP TO GATE ON DELAY V RISING THROUGH BOTH THE PROGRAMMED UVLO IN AND OVP LEVELS. GATE TURNS- THEN TURNS-OFF AS V ...
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Typical Performance Curves GATE V IN VIN VOUT FIGURE 33. BACK-TO-BACK FET TURN_ON DETAIL GATE FAST OFF, ~200ns FALL TIME ~70ns FROM 20V TO 12.6V ACROSS 57nF GATE OUTPUT SINKING ~ 6A FIGURE 35. ...
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Typical Performance Curves VIN GATE FIGURE 39. V HOT SWAPPED TO GATE WITH BIAS = 12V NO LOAD COMP ADJUST V FIGURE 41. HIGH SPEED ...
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Functional Description Functional Overview In a redundant power distribution system, similar potential and parallel power supplies each contribute to the load current through various active and passive current sharing schemes. Typically ORing power diodes are used to protect against reverse ...
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Applications Information Power-Up Considerations BIAS AND V CONSTRAINTS IN Upon power-up when the V supply is separate from the BIAS IN supply, the BIAS voltage must be greater or equal to the V voltage at all times. When using a ...
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The Figure 1 circuit shown on page 1 is the basic circuit used for ORing voltages >3V to 20V. The ISL6146A application shown in Figure 43 is the configuration for ORing very low voltages 3V. Additionally, this ...
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ISL6146 Evaluation Platforms Description and Use of the Evaluation Boards The three ISL6146 evaluation boards are to demonstrate the four application configurations discussed earlier. All the boards have ADJ shorted to VOUT with the PCB layout having the component footprints ...
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FIGURE 48. ISL6146BEVAL1Z PHOTOGRAPH FIGURE 50. ISL6146CEVAL1Z PHOTOGRAPH 19 ISL6146 FIGURE 49. ISL6146BEVAL1Z SCHEMATIC FIGURE 51. ISL6146CEVAL1Z SCHEMATIC (UVLO AND OVP TEST POINT LABELS ARE SWAPPED) FN7667.0 December 16, 2011 ...
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... CAP, SMD, 0603, 50V, 10% Test Point Banana Jack Q1 > VIN VIN GATE VOUT BIAS FLT ISL6146B ADJ EN GND MANUFACTURER PART NUMBER Intersil ISL6146AFUZ Various Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Generic Intersil ISL6146BFUZ Various Generic Generic Generic Generic ...
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... Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...
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Package Outline Drawing L8.3x3J 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0 9/09 3.00 (4X) 0.15 6 PIN 1 INDEX AREA TOP VIEW ( 2. 1.95) (1.64) ( 2.80 ) PIN 1 (6x 0.65) TYPICAL RECOMMENDED LAND ...
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Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 3.0±0. PIN TOP VIEW H 0.25 - 0.36 0. SIDE VIEW 1 (5.80) (4.40) (3.00) ...