isl6260c Intersil Corporation, isl6260c Datasheet - Page 18

• Manufacturer Part Number: isl6260c
• Description: Multiphase Pwm Regulator For Imvp-6 Mobile Cpus
• Manufacturer: Intersil Corporation

A differential amplifier allows voltage sensing for precise
voltage regulation at the microprocessor die. The inputs to
the amplifier are the VSEN and RTN pins.
B) Load Line or Droop Accomplishment
As the load current increases from zero, the output voltage
will drop from the VID table value by an amount proportional
to load current to achieve the IMVP-6 load line. The
ISL6260C provides for current to be sensed using resistors
in series with the channel inductors as shown in the
application circuit of Figure 40 or using the intrinsic series
resistance of the inductors as shown in the application circuit
of Figure 39. In both cases, signals representing the inductor
currents are summed at VSUM which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 41. The voltage at the DROOP pin minus the output
voltage at VO pin is the total load current multiplied by a gain
factor. This value is used as an input to the differential
amplifier to achieve the IMVP-6 load line as well as the input
to the overcurrent circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load-line
accuracy with reduced cost.
C) Phase Current Balance
In addition to the total current which is used for DROOP and
OCP, the individual channel average currents are also
monitored by the phase node voltage. Channel current
differences are sensed by comparing ISEN1, ISEN2, and
ISEN3 voltage. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channels to
cause the voltages presented to the ISEN pins to be equal.
D) Enable and Disable Phases
The ISL6260C controller can be configured for three-, two-or
single-channel operation. To disable channel two and/or
channel three, its PWM output pin should be tied to +5V and
the ISEN pins should be grounded. In three-channel
operation, the three channel PWM's are phase shifted by
120°, and in two-channel operation they are phase shifted by
180°.
E) Switching Frequency in CCM/DCM mode
The switching frequency is adjusted by the resistor between
the error amplifier output and the VW pin. When ISL6260C is
in continuous conduction mode (CCM), the switching
frequency may not be as constant as that of a fixed
frequency PWM controllers. However, the switching
frequency variation will be kept small to maintain the output
voltage ripple within SPEC. In general, the switching
frequency will be very close to the set value at high input
voltage and heavy load conditions.
When DPRSLPVR is high and DPRSTP# is low, the FCCM
pin will become low, and discontinuous conduction mode
18
ISL6260C
(DCM) operation will be allowed in the ISL6208 gate drive. In
DCM, ISL6208 turns off the lower FET after its channel
current across zero. As load is further reduced, channel
switching frequency will drop, providing optimized efficiency
at light loading. FCCM logic low is the signal to enable, or to
allow the DCM operation. Only if the inductor current is really
cross zero, does the true DCM occur.
Dynamic Operation
Refer to Figure 43. The ISL6260C responds to changes in
VID command voltage by slewing to new voltages with a
dV/dt set by the SOFT capacitor and by the state of
DPRSLPVR. With CSOFT = 20nF and DPRSLPVR HIGH,
the output voltage will move at ±2mV/µs for large changes in
voltage. For DPRSLPVR LOW, the large signal dV/dt will be
±10mV/µs. As the output approaches the VID command
voltage, the dV/dt rate moderates to prevent overshoot.
During Geyserville III transitions where there is one LSB VID
step each 5µs, the controller will follow the VID command
with its dV/dt rate of ±2.5mV/µs.
Keeping DPRSLPVR HIGH during VID transitions will result
in reduced dV/dt slew rate and lesser audio noise. For
fastest recovery from Deeper Sleep to Active mode,
DPRSLPVR LOW achieves higher dV/dt as required by
IMVP-6 DPRSTP# and DPRSLPVR logic SPEC.
Intersil's R
output voltage is insensitive to a fast slew input voltage
change. Refer to Figure 15 in the “Typical Operating
Performance” section of this document for Input Transient
Performance.
The hysteresis window voltage is constructed with a resistor on
the Vw pin to the error amplifier outputs. The synthesized
inductor current ripple signal compares with the window voltage
and generates PWM signal. At load current step up, the
switching frequency is increased resulting in a faster response
than conventional fixed frequency PWM controllers. As all the
phases shares the same hysteretic window voltage, it also
ensures excellent dynamic current balance between phases.
The individual average phase voltages are monitored and
controlled to achieve steady state current balance among the
phases with current balance loop.
FIGURE 43. DEEPER SLEEP TRANSITION SHOWING
D P R S LP V R
M S B of V ID
D P R S TP #
V o ut
3
intrinsically has voltage-feed-forward. The
DPRSLPVR’s EFFECT ON EXIT SLEW RATE
-2 m V /us
2 m V /u s
10 m V /us
March 6, 2009
FN9259.2