isl6530

Manufacturer Part Numberisl6530
DescriptionDual 5v Synchronous Buck Pulse-width Modulator Pwm Controller For Ddram Memory Vddq And Vtttermination
ManufacturerIntersil Corporation
isl6530 datasheet
 


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Data Sheet
Dual 5V Synchronous Buck Pulse-Width
Modulator (PWM) Controller for DDRAM
Memory V
and V
Termination
DDQ
TT
The ISL6530 provides complete control and protection for
dual DC-DC converters optimized for high-performance
DDRAM memory applications. It is designed to drive low
cost N-channel MOSFETs in synchronous-rectified buck
topology to efficiently generate 2.5V V
DDQ
DDRAM memory, V
for DDRAM differential signalling,
REF
and V
for signal termination. The ISL6530 integrates all of
TT
the control, output adjustment, monitoring and protection
functions into a single package.
The V
output of the converter is maintained at 2.5V
DDQ
through an integrated precision voltage reference. The V
output is precisely regulated to 1/2 the memory power
supply, with a maximum tolerance of ±1% over temperature
and line voltage variations. V
accurately tracks V
TT
During V2_SD sleep mode, the V
output is maintained by
TT
a low power window regulator.
The ISL6530 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes two
phase-locked 300kHz triangle-wave oscillators which are
o
displaced 90
to minimize interference between the two
PWM regulators. The regulators feature error amplifiers with
a 15MHz gain-bandwidth product and 6V/µs slew rate which
enables high converter bandwidth for fast transient
performance. The resulting PWM duty ratio ranges from 0%
to 100%.
The ISL6530 protects against over-current conditions by
inhibiting PWM operation. The ISL6530 monitors the current
in the V
regulator by using the r
DDQ
DS(ON)
MOSFET which eliminates the need for a current sensing
resistor.
Ordering Information
TEMP
o
PART NUMBER
RANGE(
C)
PACKAGE
ISL6530CB*
0 to 70
24 Lead SOIC
ISL6530CBZ*
0 to 70
24 Lead SOIC
(See Note)
(Pb-free)
ISL6530CR*
0 to 70
32 Lead 5x5 QFN
ISL6530CRZ*
0 to 70
32 Lead 5x5 QFN
(See Note)
(Pb-free)
ISL6530EVAL1, 2
Evaluation Board
* Add “-T” suffix for tape and reel option.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
November 15, 2004
Features
• Provides V
channel DDRAM memory systems
• Excellent voltage regulation
= 2.5V ±2% over full operating range
- V
DDQ
- V
= (V
REF
- V
= V
TT
for powering
• Supports ‘S3’ sleep mode
- V
is held at V
TT
to minimize wake-up time
• Fast transient response
- Full 0% to 100% duty ratio
REF
• Operates from +5V input
• Overcurrent fault monitor on VDD
- Does not require extra current sensing element
.
REF
- Uses MOSFET’s r
• Drives inexpensive N-Channel MOSFETs
• Small converter size
- 300kHz fixed frequency oscillator
• 24 Lead, SOIC or 32 Lead, 5mm×5mm QFN
• Pb-Free Available (RoHS Compliant)
Applications
• V
, V
DDQ
TT
systems
- Main Memory in AMD® Athlon™ and K8™, Pentium®
III, Pentium IV, Transmeta, PowerPC™, AlphaPC™, and
UltraSparc® based computer systems
of the upper
- Video memory in graphics systems
• High-power tracking DC-DC regulators
PKG.
DWG. #
M24.3
M24.3
L32.5x5
L32.5x5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
1-888-INTERSIL or 321-724-7143
Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6530
FN9052.2
, V
, and V
voltages for one- and two-
DDQ
REF
TT
÷2) ±1% over full operating range
DDQ
± 30mV
REF
÷2 via low power window regulator
DDQ
DS(ON)
, and VREF regulation for DDRAM memory
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved.

isl6530 Summary of contents

  • Page 1

    ... Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory V and V Termination DDQ TT The ISL6530 provides complete control and protection for dual DC-DC converters optimized for high-performance DDRAM memory applications designed to drive low cost N-channel MOSFETs in synchronous-rectified buck topology to efficiently generate 2.5V V DDQ DDRAM memory, V ...

  • Page 2

    ... FB1 COMP1 18 7 SENSE1 17 VREF_IN GNDA 15 PHASE2 BOOT2 13 UGATE2 12 2 ISL6530 PGND1 LGATE1 PVCC1 OCSET/SD PHASE 1 V2_SD VREF PGOOD COMP2 FB1 SENSE2 COMP1 FB2 SENSE1 VCC LGATE2 VREF_IN PGND2 GNDA GNDA 32 LEAD (QFN) TOP VIEW ...

  • Page 3

    ... Block Diagram PGOOD FB1 COMP1 SENSE1 VREF_IN + VREF - FB2 COMP2 SENSE2 V2_SD 3 ISL6530 OCSET/SD VCC POWER-ON RESET (POR) + SOFT- - 40µA START OVER- CURRENT PWM ERROR COMPARATOR AMP INHIBIT + + - - PWM 0.8V REFERENCE OSCILLATOR o 90 Phase Shift ERROR AMP + - PWM - + INHIBIT PWM COMPARATOR WINDOW ...

  • Page 4

    ... FB1 R FB1 SENSE1 4 ISL6530 PGOOD VCC PGOOD BOOT1 UGATE1 PHASE1 PVCC1 LGATE1 PGND1 ISL6530 BOOT2 UGATE2 PHASE2 LGATE2 PGND2 COMP2 FB2 SENSE2 R FB2 FIGURE 1. TYPICAL APPLICATION FOR ISL6530 D BOOT1 BOOT1 L OUT1 + BOOT2 BOOT2 L OUT2 DDQ ...

  • Page 5

    ... Upper Gate Source (UGATE1 and 2) Upper Gate Sink (UGATE1 and 2) Lower Gate Source (LGATE1 and 2) Lower Gate Sink (LGATE1 and 2) PROTECTION OCSET/SD Current Source OCSET/SD Disable Voltage 5 ISL6530 Thermal Information Thermal Resistance SOIC Package (Note +0.3V CC QFN Package (Note 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range ...

  • Page 6

    ... I = PEAK An overcurrent trip cycles the soft-start function. Pulling the OCSET/SD pin to ground resets the ISL6530 and all external MOSFETS are turned off allowing the two output voltage power rails to float. PGOOD A high level on this open-drain output indicates that both the ...

  • Page 7

    ... SENSE2 is used as the regulation point for the window regulator that is enabled in V2_SD mode. Functional Description Overview The ISL6530 contains control and drive circuitry for two synchronous buck PWM voltage regulators. Both regulators utilize 5V bootstrapped output topology to allow use of low cost N-channel MOSFETs. The regulators are driven by ...

  • Page 8

    ... The only load placed on the V the leakage of the associated signal pins of the DDRAM and memory controller ICs. 8 ISL6530 When the V2_SD input of the ISL6530 is driven high, the V regulator is placed into a “sleep” state. In the sleep TT state the main V VCC (5V) upper and lower MOSFETs being turned off ...

  • Page 9

    ... LOW. Upon release of the OCSET/SD pin, the IC enters into a soft start cycle which brings both outputs back into regulation. Voltage Monitoring The ISL6530 offers a PGOOD signal that will communicate whether the regulation of both V and V DDQ ±15% of regulation, the V2_SD pin is held low and the bias voltage of the IC is above the POR level ...

  • Page 10

    ... TT through protection method which allows the converter to sink current as well as source current. Care should be exercised when designing a converter with the ISL6530 when it is known that the converter may sink current. When the converter is sinking current behaving as a boost converter that is regulating its input voltage. This means that the converter is boosting current into the input rail of the regulator ...

  • Page 11

    ... OUT2 The compensation network consists of the error amplifier (internal to the ISL6530) and the impedance networks Z and closed loop transfer function with the highest 0dB crossing frequency ( the difference between the closed loop phase 180 degrees. The equations below relate the compensation network’ ...

  • Page 12

    ... The compensation gain uses external impedance networks Z and Z to provide a stable, high bandwidth (BW) overall FB IN loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. 12 ISL6530 V IN 100 OUT 80 PHASE C ...

  • Page 13

    ... MOSFET’s body diode. The gate-charge losses are dissipated by the ISL6530 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, t increases the MOSFET switching losses. ...

  • Page 14

    ... V is the bootstrap voltage immediately after turn-on. BOOT2 14 ISL6530 The bootstrap capacitor begins its refresh cycle when the gate drive begins to turn-off the upper MOSFET. A refresh cycle ends when the upper MOSFET is turned on again, which varies depending on the switching frequency and duty cycle ...

  • Page 15

    ... ISL6530 DC-DC Converter Application Circuit Figure 11 shows an application circuit for a DDR SDRAM power supply, including V (+2.5V) and V DDQ Detailed information on the circuit, including a complete Bill- V2_SD PGOOD VREF VREF_IN C 30 100pF GNDA C 26 5600pF COMP1 100pF 6.34kΩ FB1 3.01kΩ ...

  • Page 16

    Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α µ 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in ...

  • Page 17

    ... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 ISL6530 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...