st62t62cmae

Manufacturer Part Numberst62t62cmae
Description8-bit Otp/eprom/fastrom Mcus With A/d Converter, Safe Reset, Auto-reload Timer And Eeprom
ManufacturerSTMicroelectronics
st62t62cmae datasheet
 
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Page 54/72

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ST62T52CM-Auto ST62T62CM-Auto
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Table 18. Conditional Branch Instructions
Instruction
Branch If
JRC e
C = 1
JRNC e
C = 0
JRZ e
Z = 1
JRNZ e
Z = 0
JRR b, rr, ee
Bit = 0
JRS b, rr, ee
Bit = 1
:
Notes
b.
3-bit address
e.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
Table 19. Bit Manipulation Instructions
Instruction
Addressing Mode
SET b,rr
Bit Direct
RES b,rr
Bit Direct
Notes:
b.
3-bit address;
rr.
Data space register;
Table 20. Control Instructions
Instruction
Addressing Mode
NOP
Inherent
RET
Inherent
RETI
Inherent
STOP (1)
Inherent
WAIT
Inherent
Notes:
1.
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
.
Affected
*.
Not Affected
Table 21. Jump & Call Instructions
Instruction
Addressing Mode
CALL abc
Extended
JP abc
Extended
Notes:
abc. 12-bit address;
* .
Not Affected
54/72
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Bytes
Cycles
1
2
1
2
1
2
1
2
3
5
3
5
rr.
Data space register
. Affected. The tested bit is shifted into carry.
* .
Not Affected
Bytes
Cycles
2
4
2
4
* . Not<M> Affected
Bytes
Cycles
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2
1
2
1
2
1
2
1
2
Bytes
Cycles
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4
2
4
Flags
Z
C
*
*
*
*
*
*
*
*
*
*
Flags
Z
C
*
*
*
*
Flags
Z
C
*
*
*
*
*
*
*
*
Flags
Z
C
*
*
*
*