st62t65b

Manufacturer Part Numberst62t65b
Description8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer, Eeprom And Spi
ManufacturerSTMicroelectronics
st62t65b datasheet
 


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8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125 C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 128 bytes
Data EEPROM: 128 bytes (none on ST62T55B)
User Programmable Options
21 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
8-bit Timer/ Counter with 7-bit programmable
prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
8-bit A/D Converter with 13 analog inputs
8-bit Synchronous Peripheral Interface (SPI)
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
OTP
EPROM
DEVICE
(Bytes)
(Bytes)
ST62T55B
3884
-
ST62T65B
3884
-
ST62E65B
3884
April 1998
ST62T65B/E65B
PDIP28
PSO28
CDIP28W
(See end of Datasheet for Ordering Information)
EEPROM
-
128
128
ST62T55B
Rev. 2.4
1/74
1

st62t65b Summary of contents

  • Page 1

    ... ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port) DEVICE SUMMARY OTP EPROM DEVICE (Bytes) (Bytes) ST62T55B 3884 - ST62T65B 3884 - ST62E65B 3884 April 1998 ST62T65B/E65B PDIP28 PSO28 CDIP28W (See end of Datasheet for Ordering Information) EEPROM - 128 128 ST62T55B Rev. 2.4 1/74 1 ...

  • Page 2

    ... Table of Contents ST62T55B / ST62T65B/E65B . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2 CENTRAL PROCESSING UNIT ...

  • Page 3

    Table of Contents 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Table of Contents ST6255B / ST6265B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 1 ...

  • Page 5

    ... ST62xx devices are based on a building block ap- proach: a common core is surrounded by a number of on-chip peripherals. The ST62E65B is the erasable EPROM version of the ST62T65B device, which may be used to em- ulate the ST62T55B and ST62T65B device, as well as the respective ST6255B and ST6265B ROM devices. ...

  • Page 6

    ... ST62T55B ST62T65B/E65B 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins ...

  • Page 7

    ... MEMORY 0FF0h INTERRUPT & RESET VECTORS 0FFFh ST62T55B ST62T65B/E65B Briefly, Program space contains user program code in OTP and user vectors; Data space con- tains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. ...

  • Page 8

    ... ST62T55B ST62T65B/E65B MEMORY MAP (Cont’d) 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register) ...

  • Page 9

    ... Table 1. Additional RAM/EEPROM Banks Device RAM EEPROM ST62T55BB bytes ST62T65B/E65B bytes bytes ST62T55B ST62T65B/E65B Table 2. ST62T55B, ST62T65B and ST62E65B Data Memory Space RAM and EEPROM DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTE R DATA RAM 60 BYTES PORT A DATA REGISTER ...

  • Page 10

    ... ST62T55B ST62T65B/E65B MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- dress 0000h and 0FFFh (top memory address de- pends on the specific device) ...

  • Page 11

    ... Data Space. The number of banks has to be load the DRBR register and the instruction has to point to the selected location was in bank 0 (from 00h address to 3Fh address). ST62T55B ST62T65B/E65B Register This register is not cleared during the MCU initiali- zation, therefore it must be written before the first access to the Data Space bank region ...

  • Page 12

    ... ST62T55B ST62T65B/E65B MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 4. EEPROM locations are accessed di- rectly by addressing these paged sections of data space ...

  • Page 13

    ... E2PAR1 bit will be un- affected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set. ST62T55B ST62T65B/E65B EEPROM Control Register (EECTL) Address: EAh — Read/Write Reset status: 00h 7 ...

  • Page 14

    ... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V 0 programming flow of the ST62T65B/E65B is de- scribed in the User Manual of the EPROM Pro- - gramming Board. The MCUs can be programmed ST62E6xB EPROM programming tools available from SGS-THOMSON ...

  • Page 15

    ... It is thus recommended that the window of the MCUs packages be covered by an opaque label to ST62T55B ST62T65B/E65B prevent unintentional erasure problems when test- ing the application in such an environment. The recommended erasure procedure of the MCUs EPROM is the exposure to short wave ul- traviolet light which have a wave-length 2537A ...

  • Page 16

    ... ST62T55B ST62T65B/E65B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in 6; the controller being externally linked to ...

  • Page 17

    ... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T55B ST62T65B/E65B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...

  • Page 18

    ... ST62T55B ST62T65B/E65B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor (R ). NET 8 illustrates various possible oscillator configura- ...

  • Page 19

    ... MAIN OSCILLATOR OSCILLATOR DIVIDE R OSCout RS0, RS1 ST62T55B ST62T65B/E65B Note: Care is required when handling the OSCR register as some bits are write only. For this rea- son not allowed to change the OSCR contents while executing interrupt service routine, as the 0 service routine cannot save and then restore its previous content ...

  • Page 20

    ... ST62T55B ST62T65B/E65B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...

  • Page 21

    ... RESET 2.8k ON RESET POWER WATCHDOG RESET ST62T55B ST62T65B/E65B in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The in- itialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction ...

  • Page 22

    ... ST62T55B ST62T65B/E65B RESETS (Cont’d) Table 6. Register Reset Status Register Oscillator Control Register 0DCh EEPROM Control Register 0EAh Port Data Registers 0C0h to 0C2h Port Direction Register 0C4h to 0C6h Port Option Register 0CCh to 0CEh Interrupt Option Register 0C8h TIMER Status/Control 0D4h AR TIMER Mode Control Register ...

  • Page 23

    ... Table 7. Recommended Option Choices Functions Required Stop Mode & Watchdog Stop Mode Watchdog ST62T55B ST62T65B/E65B When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU. In the HARDWARE option, the Watchdog is per- manently enabled. Since the oscillator will run con- tinuously, low power mode is not available ...

  • Page 24

    ... ST62T55B ST62T65B/E65B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR) . This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits T5, and the SR bit are all set to “ ...

  • Page 25

    ... LSB of the Watchdog downcounter and bit-2 (T5) is the MSB. These bits are set to “1” on Reset. ST62T55B ST62T65B/E65B 3.3.2 Application Notes The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible ...

  • Page 26

    ... ST62T55B ST62T65B/E65B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are ex- ecuted after activation, before the Watchdog can generate a Reset ...

  • Page 27

    ... MCU from STOP/WAIT modes. Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automat- ST62T55B ST62T65B/E65B ically reset by the core at the beginning of the non- maskable interrupt service routine. Interrupt request from source #1 can be config- ...

  • Page 28

    ... ST62T55B ST62T65B/E65B IINTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...

  • Page 29

    ... Port PBn ORPB-DRPB C1h-C5h Port PCn ORPC-DRPC C2h-C6h ST62T55B ST62T65B/E65B Bit 5 = ESB: Edge Selection bit . The bit ESB selects the polarity of the interrupt source #2. Bit 4 = GEN: Global Enable Interrupt . When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding NMI) are disabled ...

  • Page 30

    ... ST62T55B ST62T65B/E65B INTERRUPTS (Cont’d) Figure 17. Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B Bits PORT C PBE Bits SPIDIV Register SPINT bit IOR REG. C8H, bit 5 SPIE bit OVF SPIMOD Register OVIE CPF AR TIMER CPIE ...

  • Page 31

    ... Watchdog), the MCU enters a normal reset proce- dure interrupt is generated during WAIT mode, the MCU’s behaviour depends on the state ST62T55B ST62T65B/E65B of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following para- graphs ...

  • Page 32

    ... ST62T55B ST62T65B/E65B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state ...

  • Page 33

    ... OPTION REGISTER S OUT TO INTE RRUPT TO ADC ST62T55B ST62T65B/E65B be also written by user software, in conjunction with the related option registers, to select the dif- ferent input mode options. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will direct- ly affect the Port data register causing an unde- sired change of the input configuration ...

  • Page 34

    ... ST62T55B ST62T65B/E65B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table 11 illustrates the various port configurations which can be selected by user soft- ware ...

  • Page 35

    ... Open Drain Output Push-pull Note *. xxx = DDR, OR, DR Bits respectively ST62T55B ST62T65B/E65B outputs advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data regis- ...

  • Page 36

    ... ST62T55B ST62T65B/E65B I/O PORTS (Cont’d) Table 12. I/O Port Option Selections MODE AVAILABLE ON PA0-PA7 Input PB0-PB5, PB6-PB7 PC0-PC4 PA0-PA7 Input PB0-PB5, PB6-PB7 with pull up PC0-PC4 Input PA0-PA7 with pull up PB0-PB5, PB6-PB7 PC0-PC4 with interrupt PA0-PA7 Analog Input PC0-PC4 Open drain output PA0-PA7 5mA ...

  • Page 37

    ... I/O PORTS (Cont’d) Figure 20. Peripheral Interface Configuration of SPI, Timer 1 and AR Timer V DD PC3/Sout PC2/Sin PC4/SCK PC1/TIM1 ARTIMin ARTIMout ST62T55B ST62T65B/E65B PP/OD OUT 1 MUX MISC. REGISTER CLOCK IN CLOCK OUT 1 MUX 0 DR SPCLK MOD REGISTER TOUT OUT 1 MUX 0 DR ARTIMin DR AR TIMER ...

  • Page 38

    ... ST62T55B ST62T65B/E65B 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 The peripheral may be configured in three different operating modes. 21 shows the Timer Block Diagram. The external TIMER pin is available to the user. The content of ...

  • Page 39

    ... BIT0 BIT1 BIT2 ST62T55B ST62T65B/E65B The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high ...

  • Page 40

    ... ST62T55B ST62T65B/E65B TIMER (Cont’d) 4.2.3 Application Notes The user can select the presence of an on-chip pull-up on the TIMER pin as option. TMZ is set when the counter reaches zero; howev- er, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. ...

  • Page 41

    ... The clock input to the AR counter is enabled by the TEN (Timer Enable) bit in the ARMC register. When TEN is reset, the AR counter is stopped and ST62T55B ST62T65B/E65B the prescaler and counter contents are frozen. When TEN is set, the AR counter runs at the rate of the selected clock source. The counter is cleared on system reset ...

  • Page 42

    ... ST62T55B ST62T65B/E65B AUTO-RELOAD TIMER (Cont’d) Figure 23 Timer Block Diagram f INT M f 7-Bit /3 INT U AR PRESCALER X PS0-PS2 CC0-CC1 PB6/ ARTIMin SL0-SL1 EF RELOAD/CAPTURE SYNCHRO 42/74 42 DATA BUS 8 DRB7 AR COMPARE REGISTER 8 CPF COMPARE OVF OVF OVIE 8-Bit LOAD AR COUNTER TCLD EIE EF 8 CPF ...

  • Page 43

    ... VALUE RELOAD REGISTER 000 PWM OUTPUT ST62T55B ST62T65B/E65B The ARTC counter is initialized by writing to the ARRC register and by then setting the TCLD (Tim- er Load) and the TEN (Timer Clock Enable) bits in the Mode Control register, ARMC. Enabling and selection of the clock source is con- trolled by the CC0, CC1, SL0 and SL1 bits in the Status Control Register, ARSC1 ...

  • Page 44

    ... ST62T55B ST62T65B/E65B AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation . In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from the counter to the ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Con- trol bits SL0, SL1 in the ARSC1 register ...

  • Page 45

    ... Bit 2 = OVIE: Overflow Interrupt . This bit, when set, enables the overflow interrupt request. If OVIE is reset, the compare interrupt request is masked. If OVIE is set and the related flag, OVF in the ST62T55B ST62T65B/E65B ARSC0 register is also set, an interrupt request is generated. Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0 . ...

  • Page 46

    ... ST62T55B ST62T65B/E65B AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 SL0 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is not affected by these bits. The prescaler division ratio is listed in the following table: Table 15 ...

  • Page 47

    ... If PDS=“1”, the A/D is powered and en- abled for conversion. This bit must be set at least one instruction before the beginning of the conver- ST62T55B ST62T65B/E65B sion to allow stabilisation of the A/D converter. This action is also needed before entering WAIT mode, since the A/D comparator is not automati- cally disabled in WAIT mode ...

  • Page 48

    ... ST62T55B ST62T65B/E65B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply voltages used as analog references. ...

  • Page 49

    ... DIVIDER CLOCK SCK FILTER FILTER Sin ST62T55B ST62T65B/E65B mode is defined by the serial clock being supplied externally on the SCK pin by the external Master device. For maximum versatility the SPI may be pro- grammed to sample data either on the rising or on the falling edge of SCK, with or without phase shift (clock Polarity and Phase selection) ...

  • Page 50

    ... ST62T55B ST62T65B/E65B SERIAL PERIPHERAL INTERFACE SPI(Cont’d) 4.5.1 SPI Registers SPI Mode Control Register (MOD) Address: E2h — Read/Write Reset status: 00h 7 SPRUN SPIE CPHA SPCLK SPIN SPSTRT The MOD register defines and controls the trans- mission modes and characteristics. This register is read/write and all bits are cleared at reset ...

  • Page 51

    ... Baud is possible (8MHz/13/64). Other Baud rates are available by proportionally selecting division fac- tors depending on CPU clock frequency. Data setup time on Sin is typically 250ns min, while data hold time is typically 50ns min. ST62T55B ST62T65B/E65B Table 18. Burst Mode Bit Clock Periods DIV6-DIV3 ...

  • Page 52

    ... ST62T55B ST62T65B/E65B SERIAL PERIPHERAL INTERFACE SPI(Cont’d) 4.6 SPI Timing Diagrams Figure 27. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal SPRUN SCK Sin Sampling Sout b7 b6 Figure 28. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal SPRUN SCK Sin Sampling Sout b7 b6 52/ ...

  • Page 53

    ... SERIAL PERIPHERAL INTERFACE SPI(Cont’d) Figure 29. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted SPRUN SCK Sin Sampling Sout b7 b6 Figure 30. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted SPRUN SCK Sin Sampling Sout b7 b6 ST62T55B ST62T65B/E65B VR0B1694 b1 b0 VR0C1694 53/74 53 ...

  • Page 54

    ... ST62T55B ST62T65B/E65B 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction ...

  • Page 55

    ... Data space register . Affected * . Not Affected ST62T55B ST62T65B/E65B Load & Store . These instructions use one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes. ...

  • Page 56

    ... ST62T55B ST62T65B/E65B INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space memory con- Table 20. Arithmetic & Logic Instructions ...

  • Page 57

    ... JP abc Extended Notes: abc. 12-bit address Not Affected ST62T55B ST62T65B/E65B Control Instructions. The control instructions control the MCU operations during program exe- cution. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. ...

  • Page 58

    ... ST62T55B ST62T65B/E65B Opcode Map Summary.The following table contains an opcode map for the instructions used by the ST6 LOW 0000 0001 0010 HI 2 JRNZ 4 CALL 2 JRNC abc e 0000 1 pcr 2 ext 1 2 JRNZ 4 CALL 2 JRNC abc e 0001 1 pcr 2 ext 1 2 JRNZ 4 ...

  • Page 59

    ... Extended nn 1 byte immediate data b.d Bit Direct abc 12 bit address bt Bit Test ee 8 bit Displacement pcr Program Counter Relative ind Indirect ST62T55B ST62T65B/E65B 1011 1100 1101 1110 RES 2 JRZ 4 LDI 2 b0,rr e rr,nn pcr 2 b.d 1 pcr 3 imm 1 SET 2 ...

  • Page 60

    ... ST62T55B ST62T65B/E65B 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V ...

  • Page 61

    ... GUARANTEED IN 7 THIS AREA 2.5 3 3.5 SUPPLY VOLTAGE (V The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. ST62T55B ST62T65B/E65B Value Test Condition s Min. Typ. 6 Suffix Version -40 1 Suffix Version 0 3 Suffix Version - 2MHz 3.0 ...

  • Page 62

    ... ST62T55B ST62T65B/E65B 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage Hys All Input pins V DD Low Level Output Voltage V DD All Output pins ...

  • Page 63

    ... IN Analog Input Current During Conversion AC Analog Input Capacitance IN Notes: 1. Noise <10mV Wit h oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased. ST62T55B ST62T65B/E65B Test Conditions Min. 100 100 100 125 Acceptance ...

  • Page 64

    ... ST62T55B ST62T65B/E65B 6.6 TIMER CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter f Input Frequency on TIMER Pin IN t Pulse Width at TIMER Pin W 6.7 SPI CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) A Symbol Parameter F Clock Frequency CL t Set-up Time SU t Hold Time h 6.8 ARTIMER ELECTRICAL CHARACTERISTICS (T = -40 to +125 C unless otherwise specified) ...

  • Page 65

    ... GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 32. 28-Pin Plastic Dual In-Line Package, 600-mil Width See Lead Detail N/2 Figure 33. 28-Pin Plastic Small Outline Package, 300-mil Width ST62T55B ST62T65B/E65B mm Dim. Min Typ A 4.445 ...

  • Page 66

    ... ST62T55B ST62T65B/E65B PACKAGE MECHANICAL DATA (Cont’d) Figure 34. 28-Ceramic Dual In Line Package, 600-mil Width 7.2 .ORDERING INFORMATION Table 25. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62E65BF1 3884 (EPROM) ST62T55BB6 ST62T55BB3 3884 (OTP) ST62T55BM6 ST62T55BM3 ST62T65BB6 ST62T65BB3 3884 (OTP) ST62T65BM6 ST62T65BM3 ...

  • Page 67

    R 8-BIT FASTROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability ...

  • Page 68

    ... ST62P55B ST62P65B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62P55B and ST62P65B are the Factory A dvanced S ervice T echnique ROM (FASTROM) versions of ST62T55B and ST62T65B OTP devic- es. They offer the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version ...

  • Page 69

    ST62P55B and ST62P65B FASTROMMICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . ...

  • Page 70

    ST62P55B ST62P65B Notes: 70/74 70 ...

  • Page 71

    R 8-BIT ROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability ...

  • Page 72

    ... ST6255B ST6265B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6255B and ST6265B is mask programmed ROM version of ST62T55B and ST62T65B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form 0 ...

  • Page 73

    ST6255B and ST6265B MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . ...

  • Page 74

    ST6255B ST6265B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask ...