s908gr32ag3vfa Freescale Semiconductor, Inc, s908gr32ag3vfa Datasheet - Page 142

• Manufacturer Part Number: s908gr32ag3vfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Input/Output (I/O) Ports
12.5.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the seven port C pins. Each bit is individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRC is configured for output mode.
PTCPUE6–PTCPUE0 — Port C Input Pullup Enable Bits
12.6 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port. PTD0 is shared with the MCLK output.
12.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
PTD7–PTD0 — Port D Data Bits
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
142
These writable bits are software programmable to enable pullup devices on an input port bit.
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
The PTD5/T2CH1–PTD4/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0 pins are timer channel
I/O pins or general-purpose I/O pins. See
Timer Interface Module
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
Alternate Function:
Address:
Reset:
Read:
Write:
Address:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Reset:
Read:
Write:
Figure 12-12. Port C Input Pullup Enable Register (PTCPUE)
$000E
Bit 7
0
0
T2CH1
$0003
PTD7
Bit 7
(TIM2).
= Unimplemented
PTCPUE6
Figure 12-13. Port D Data Register (PTD)
6
0
T2CH0
PTD6
6
PTCPUE5
5
0
T1CH1
PTD5
Chapter 17 Timer Interface Module (TIM1)
5
PTCPUE4
4
0
T1CH0
Unaffected by reset
PTD4
4
PTCPUE3
3
0
SPSCK
PTD3
3
PTCPUE2
2
0
PTD2
MOSI
2
PTCPUE1
1
0
PTD1
MISO
1
Freescale Semiconductor
PTCPUE0
Bit 0
0
and
MCLK
PTD0
Bit 0
SS
Chapter 18